Commits · c3f6b2806f2a73e3b98d6c2e3aa36b0e8795eef7 · Roger Ferrer / llvm-epi · GitLab

Aug 14, 2017
- Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."" · c3f6b280
  Simon Dardis authored Aug 14, 2017
  c3f6b280
- Reland "[mips][mt][6/7] Add support for mftr, mttr instructions." · cbf55dea
  Simon Dardis authored Aug 14, 2017
  cbf55dea
Aug 13, 2017
- [COFF, ARM64] Use '//' as comment character in assembly files in GNU environments · 23413195
  Martin Storsjö authored Aug 13, 2017
  23413195
- [X86][AsmParser][AVX512] Error appropriately when K0 is tried as a write-mask · 799fa2c7
  Coby Tayree authored Aug 13, 2017
  799fa2c7
Aug 11, 2017
- [AArch64] Enable ARMv8.3-A pointer authentication · 6d42de78
  Sam Parker authored Aug 11, 2017
  6d42de78
- [ARM] Assembler support for the ARMv8.2a dot product instructions · 7426c97b
  Sjoerd Meijer authored Aug 11, 2017
  7426c97b
Aug 10, 2017
- Revert "[AsmParser] Hash is not a comment on some targets" · a24e4cda
  Ahmed Bougacha authored Aug 10, 2017
  a24e4cda
- [AArch64] Assembler support for v8.3 RCpc · 71a474d5
  Sam Parker authored Aug 10, 2017
  71a474d5
Aug 09, 2017
- [AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodes · 1e32550d
  Dmitry Preobrazhensky authored Aug 09, 2017
  1e32550d
- [X86][Asm]Allow far jmp/call to be picked when using explicit FWORD size specifier · 36386553
  Coby Tayree authored Aug 09, 2017
  36386553
- [AArch64] Assembler support for the ARMv8.2a dot product instructions · 79876332
  Sjoerd Meijer authored Aug 09, 2017
  79876332
- [AsmParser][AVX512]Enhance OpMask/Zero/Merge syntax check rubostness · 3bfb365f
  Coby Tayree authored Aug 09, 2017
  3bfb365f
- [AsmParser] Hash is not a comment on some targets · 7f569a2d
  Oliver Stannard authored Aug 09, 2017
  7f569a2d
Aug 08, 2017
- Revert "[ARM] Fix assembly and disassembly for VMRS/VMSR" · f370f2e3
  Tim Northover authored Aug 08, 2017
  f370f2e3
Aug 07, 2017
- AMDGPU: Remove -mcpu=SI · 36b4b0be
  Matt Arsenault authored Aug 07, 2017
  36b4b0be
- [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI · 50805a0b
  Dmitry Preobrazhensky authored Aug 07, 2017
  50805a0b
- [ARM] Fix assembly and disassembly for VMRS/VMSR · 7dffb9bf
  Andre Vieira authored Aug 07, 2017
  7dffb9bf
Aug 04, 2017
- [AMDGPU][MC] Enabled expressions as operands · 4b11a78a
  Dmitry Preobrazhensky authored Aug 04, 2017
  4b11a78a
Aug 02, 2017
- Don't pass the code model to MC · 9f929957
  Rafael Espindola authored Aug 02, 2017
  9f929957
- [AsmParser][GAS-compatibility] Ignore an empty 'p2align' directive · d483a107
  Coby Tayree authored Aug 02, 2017
  d483a107
Jul 29, 2017
- [AArch64] Tie source and destination operands for AESMC/AESIMC. · f63a5e91
  Florian Hahn authored Jul 29, 2017
  f63a5e91
Jul 26, 2017
- [COFF, ARM64] Fix symbol offsets in ADRP/ADD/LDR/STR relocations · 0b7bf7a2
  Martin Storsjö authored Jul 26, 2017
  0b7bf7a2
Jul 25, 2017
- [AArch64] Update a comment in a test · 1913360a
  Martin Storsjö authored Jul 25, 2017
  1913360a
- [Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed · 7856a320
  Fedor Sergeev authored Jul 25, 2017
  7856a320
- X86 Asm uses assertions instead of proper diagnostic. This patch fixes that. · 32e9b1ad
  Andrew V. Tischenko authored Jul 25, 2017
  32e9b1ad
Jul 22, 2017
- [X86] Add nopq instruction which is a rex encoded version of nopl for gas compatibility. · abfe380f
  Craig Topper authored Jul 22, 2017
  abfe380f
- [X86] Add register form of NOPL and NOPW for assembler/disassembler. · e88aef4b
  Craig Topper authored Jul 22, 2017
  e88aef4b
Jul 21, 2017
- AMDGPU: Add instruction definitions for some scratch_* instructions · ca7b0a17
  Matt Arsenault authored Jul 21, 2017
  ca7b0a17
- [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier · abf28394
  Dmitry Preobrazhensky authored Jul 21, 2017
  abf28394
Jul 20, 2017
- [COFF, ARM64, CodeView] Add support to emit CodeView debug info for ARM64 COFF · d41ac895
  Mandeep Singh Grang authored Jul 20, 2017
  d41ac895
- AMDGPU: Add encoding for carryless add/sub instructions · c37fe66e
  Matt Arsenault authored Jul 20, 2017
  c37fe66e
- AMDGPU: Add encodings for global atomics · f65c5ac9
  Matt Arsenault authored Jul 20, 2017
  f65c5ac9
- revert: [llvm] r308609 - This patch added some test cases to demonsrate the... · ba7b22cd
  Simon Pilgrim authored Jul 20, 2017
  ba7b22cd
- This patch added some test cases to demonsrate the issues described in Bug... · 64319627
  Andrew V. Tischenko authored Jul 20, 2017
  64319627
- AMDGPU: Correct encoding for global instructions · 04004716
  Matt Arsenault authored Jul 20, 2017
  04004716
Jul 19, 2017
- [AArch64] Force relocations for all ADRP instructions · b2e9fcfc
  Martin Storsjö authored Jul 19, 2017
  b2e9fcfc
- [AArch64, COFF] Interpret .align as power of two for COFF as well · 2ff5f5d6
  Martin Storsjö authored Jul 19, 2017
  2ff5f5d6
- [ARM] Unify handling of M-Class system registers · 2cb0c950
  Javed Absar authored Jul 19, 2017
  2cb0c950
Jul 18, 2017
- [AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if... · 4685b70a
  Sam Kolton authored Jul 18, 2017
  4685b70a
- [AMDGPU][MC] Corrected disassembler for proper decoding of v_mqsad_u32_u8 · 30fc5239
  Dmitry Preobrazhensky authored Jul 18, 2017
  30fc5239