Commits · d23e4f6872c6c19c210efa9fcd19e43942ddf465 · Roger Ferrer / llvm-epi · GitLab

May 03, 2021
- [RISCV] Add support for fmin/fmax vector reductions · d23e4f68
  Fraser Cormack authored Apr 29, 2021
  d23e4f68
May 02, 2021
- [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. · ba63cdb8
  Craig Topper authored May 02, 2021
  ba63cdb8
Apr 30, 2021
- [RISCV][NFC] Merge RV32/RV64 test checks with a common prefix · 1d85b247
  Fraser Cormack authored Apr 30, 2021
  
  1d85b247
- [RISCV] Support STEP_VECTOR with a step greater than one · 791766e6
  Fraser Cormack authored Apr 20, 2021
  791766e6
- [RISCV] Fix StackOffset calculation when using sp to access the fixed stack... · 5603ed60
  luxufan authored Apr 12, 2021
  5603ed60
- [RISCV] Precommit a test case that test accessing a fixed object when has rvv vector object existed · 325b454e
  luxufan authored Apr 12, 2021
  325b454e
Apr 29, 2021
- [RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) ->... · dcdda2bd
  Craig Topper authored Apr 29, 2021
  dcdda2bd
- [RISCV] Add test cases for D101485. NFC · 60216ade
  Craig Topper authored Apr 29, 2021
  
  60216ade
- [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32. · 0c330afd
  Craig Topper authored Apr 29, 2021
  0c330afd
- [RISCV] Teach computeKnownBits that vsetvli returns number less than 2^31. · 25391cec
  Craig Topper authored Apr 29, 2021
  25391cec
- [RISCV][NFC] Combine identical RV32 and RV64 test checks · f6c54a61
  Fraser Cormack authored Apr 29, 2021
  
  f6c54a61
- [RISCV] Fix stack slot for argument types (Bug 49500) · 43ad058a
  Fraser Cormack authored Mar 22, 2021
  43ad058a
Apr 27, 2021
- [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing... · ce09dd54
  Craig Topper authored Apr 27, 2021
  ce09dd54
- [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. · 262a72f5
  Craig Topper authored Apr 26, 2021
  262a72f5
Apr 26, 2021
- [RISCV] Match splatted load to scalar load + splat. Form strided load during isel. · e2cd92cb
  Craig Topper authored Apr 26, 2021
  e2cd92cb
- [RISCV] Optimize addition with immediate · 60ed86d3
  Ben Shi authored Apr 26, 2021
  60ed86d3
- [RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs. · 8f5cd494
  Craig Topper authored Apr 25, 2021
  8f5cd494
- [RISCV] [1/2] Add IR intrinsic for Zbe extension · 8cf54c7f
  Levy Hsu authored Apr 25, 2021
  8cf54c7f
Apr 23, 2021
- [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. · 3064a63b
  Craig Topper authored Apr 23, 2021
  3064a63b
- [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max) · 83b8f8da
  Fraser Cormack authored Apr 22, 2021
  83b8f8da
- [RISCV] [1/2] Add IR intrinsic for Zbp extension · b49337bb
  Levy Hsu authored Apr 22, 2021
  b49337bb
- [RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases. · 5185b529
  Craig Topper authored Apr 22, 2021
  5185b529
Apr 22, 2021
- [RISCV] Add IR intrinsics for vmsge(u).vv/vx/vi. · e01c419e
  Craig Topper authored Apr 22, 2021
  e01c419e
- [RISCV] Add missing tests for vector type for second operand of vmsgt and vmsgtu IR intrinsics. · d77d56ac
  Craig Topper authored Apr 22, 2021
  d77d56ac
- [RISCV] Support vector type for second operand of vmfge and vmfgt IR intrinsics. · 9524a055
  Craig Topper authored Apr 22, 2021
  9524a055
- [RISCV] Turn splat shuffles of vector loads into strided load with stride of x0. · 70254ccb
  Craig Topper authored Apr 22, 2021
  70254ccb
- [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. · 77f14c96
  Craig Topper authored Apr 22, 2021
  77f14c96
- [DAGCombiner] Allow operand of step_vector to be negative. · 978eb3f1
  Jun Ma authored Apr 19, 2021
  978eb3f1
- [RISCV] Custom lowering of SET_ROUNDING · 740962e5
  Serge Pavlov authored Nov 10, 2020
  740962e5
- [RISCV] Custom lowering of FLT_ROUNDS_ · 6e63dfda
  Serge Pavlov authored Nov 05, 2020
  6e63dfda
- [RISCV] Teach lowerSPLAT_VECTOR_PARTS to detect cases where Hi is sign extended from Lo. · f6d8cf77
  Craig Topper authored Apr 21, 2021
  f6d8cf77
Apr 21, 2021
- [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines · c141bd3c
  Fraser Cormack authored Apr 20, 2021
  c141bd3c
- [RISCV] Further fixes for RVV stack offset computation · 3f02d269
  Fraser Cormack authored Apr 20, 2021
  3f02d269
- [RISCV] Add missing SEW=64 tests to vmslt-rv32.ll. NFC · 78abad56
  Craig Topper authored Apr 20, 2021
  
  78abad56
Apr 20, 2021
- [RISCV][NFC] Add tests for scalable-vector DAGCombiner improvements · 60622b82
  Fraser Cormack authored Apr 20, 2021
  60622b82
- [RISCV] Fix missing emergency slots for scalable stack offsets · b4a358a7
  Fraser Cormack authored Apr 15, 2021
  b4a358a7
- [DAGCombiner] Support fold zero scalar vector. · 1ef5699d
  Jun Ma authored Apr 20, 2021
  1ef5699d
- [SelectionDAG] Relax constraints on STEP_VECTOR step operand · 457da7f2
  Fraser Cormack authored Apr 14, 2021
  457da7f2
- [RISCV][test] Add a new test of addition · b7249bf3
  Ben Shi authored Apr 20, 2021
  b7249bf3
Apr 19, 2021
- [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte. · 7ed01a42
  Craig Topper authored Apr 19, 2021
  7ed01a42