Commits · d35fcf0e97e7bb02381506a71e61ec282b292c50 · Roger Ferrer / llvm-epi · GitLab

Nov 05, 2022
- [RISCV] Add isel pattern for (and X, 0xffffffff << C) with Zba. · 91aa233b
  Craig Topper authored Nov 04, 2022
  91aa233b
Nov 02, 2022
- Revert "[RISCV] Enable the LocalStackSlotAllocation pass support" · dc452a76
  Craig Topper authored Nov 01, 2022
  dc452a76
Nov 01, 2022
- [VP][RISCV] Add vp.rint and RISC-V support. · 71e4e355
  Yeting Kuo authored Oct 24, 2022
  71e4e355
Oct 31, 2022
- [RISCV] Fix crash a vector add has a 4x sext and zext operand. · 2a827e4a
  Craig Topper authored Oct 31, 2022
  2a827e4a
Oct 29, 2022
- [DAG] Enable combineShiftOfShiftedLogic folds after type legalization · 78739fdb
  Simon Pilgrim authored Oct 29, 2022
  78739fdb
Oct 28, 2022
- [RISCV] Optimize i64 insertelt on RV32. · 6a794419
  Craig Topper authored Oct 28, 2022
  6a794419
- [RISCV] Adjust RV64I data layout by using n32:64 in layout string · 974e2e69
  Craig Topper authored Oct 28, 2022
  974e2e69
- [DAG] visitXOR - fold XOR(A,B) -> OR(A,B) iff A and B have no common bits · d47f056c
  Simon Pilgrim authored Oct 28, 2022
  d47f056c
Oct 27, 2022
- [RISCV] Fix an obvious CSE opportunity in LSR test case. NFC · 8fa32a74
  Craig Topper authored Oct 27, 2022
  
  8fa32a74
- [LegalizeVectorOps][X86][RISCV] Expand vector S/USHLSAT instead of unrolling. · 00d93def
  Craig Topper authored Oct 27, 2022
  00d93def
Oct 26, 2022
- [RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven. · e94dc58d
  Craig Topper authored Oct 26, 2022
  e94dc58d
- [RISCV] Add tests for fixed vector sshl_sat/ushl_sat. NFC · 0a03240f
  Craig Topper authored Oct 26, 2022
  
  0a03240f
- [RISCV] add svinval extension · 7d7940fd
  Piyou Chen authored Oct 26, 2022
  7d7940fd
- [RISCV] Use vslide1down for i64 insertelt on RV32. · a61b7488
  Craig Topper authored Oct 26, 2022
  a61b7488
Oct 25, 2022
- [RISCV] Add shift amount operands of shift, rotate, and Zbs instructions to hasAllNBitUsers. · a54f3347
  Craig Topper authored Oct 24, 2022
  
  a54f3347
- [RISCV] Add ORI to hasAllNBitUsers. · 223f466f
  Craig Topper authored Oct 24, 2022
  223f466f
Oct 24, 2022
- Recommit "[TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant." · 1fa8fd4c
  Craig Topper authored Oct 24, 2022
  1fa8fd4c
- Revert "[TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant." · 65aaecca
  Craig Topper authored Oct 24, 2022
  65aaecca
- [RISCV] Add Svnapot extension · f8b84268
  Piyou Chen authored Oct 24, 2022
  f8b84268
Oct 23, 2022
- [RISCV] Make selectShiftMask look for negate opportunities after looking through AND. · a41c1f31
  Craig Topper authored Oct 23, 2022
  a41c1f31
- [TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant. · f6a7b478
  Craig Topper authored Oct 22, 2022
  f6a7b478
- Revert "[DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y))" · db25f51e
  Craig Topper authored Oct 22, 2022
  db25f51e
- [DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y)) · e8b3ffa5
  Craig Topper authored Oct 22, 2022
  e8b3ffa5
- [DAGCombiner][RISCV] Make foldBinOpIntoSelect work correctly with opaque constants. · 00816714
  Craig Topper authored Oct 22, 2022
  00816714
Oct 22, 2022
- [RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel. · 4830fa18
  Craig Topper authored Oct 22, 2022
  4830fa18
Oct 21, 2022
- [MachineCombiner][RISCV] Relax optimization level requirement · 14a5b9cd
  Anton Sidorenko authored Oct 19, 2022
  14a5b9cd
Oct 20, 2022
- [MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with... · 2c82080f
  Craig Topper authored Oct 20, 2022
  2c82080f
- [VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum. · 55ae180a
  Yeting Kuo authored Oct 12, 2022
  55ae180a
- [RISCV] Remove -enable-unsafe-fp-math from machine combiner tests. NFC · 061566d9
  Craig Topper authored Oct 19, 2022
  061566d9
Oct 19, 2022
- [RISCV] Add more check prefixes to extractelt-fp.ll to fix a conflicting case. · e0afb72e
  Craig Topper authored Oct 19, 2022
  e0afb72e
- [RISCV] Enable the LocalStackSlotAllocation pass support · 82c820b9
  luxufan authored Oct 19, 2022
  82c820b9
Oct 18, 2022
- [RISCV] Lower VECTOR_SHUFFLE to VSLIDEDOWN_VL. · 615af94d
  Han-Kuan Chen authored Oct 17, 2022
  615af94d
- [RISCV] Pre-commit tests for lowering VECTOR_SHUFFLE to VSLIDEDOWN_VL. · 8d0246a9
  Han-Kuan Chen authored Oct 17, 2022
  8d0246a9
- [MachineCombiner][RISCV] Enable MachineCombiner for RISCV · 1978b4d9
  Anton Sidorenko authored Oct 17, 2022
  1978b4d9
- Revert "[MachineCombiner][RISCV] Enable MachineCombiner for RISCV" · e175f99c
  Anton Afanasyev authored Oct 18, 2022
  e175f99c
- [MachineCombiner][RISCV] Enable MachineCombiner for RISCV · 3112cf3b
  Anton Sidorenko authored Oct 17, 2022
  3112cf3b
- [MachineCombiner][RISCV] Precommit test for D135264 · bd6bf349
  Anton Sidorenko authored Sep 15, 2022
  
  bd6bf349
- [RISCV] Optimize SELECT_CC when the true value of select is Constant · 7b970290
  LiaoChunyu authored Oct 18, 2022
  7b970290
Oct 17, 2022
- [RISCV] Add basic support for the sifive-7-series short forward branch optimization. · 2b32e4f9
  Craig Topper authored Oct 17, 2022
  2b32e4f9
- [TargetLowering][RISCV][Sparc] Don't emit zero check in CTTZTableLookup for CTTZ_ZERO_UNDEF. · 30305d79
  Craig Topper authored Oct 17, 2022
  30305d79