Commits · d3738a09fb2587f584cec5faefda1f37743524a5 · Roger Ferrer / llvm-epi · GitLab

Jul 21, 2021
- [RISCV][test] Add tests for mul optimization in the zba extension with SH*ADD · d3738a09
  Ben Shi authored Jul 21, 2021
  d3738a09
Jul 20, 2021
- [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace... · 81efb825
  Craig Topper authored Jul 20, 2021
  81efb825
- [RISCV] Add -mattr=+c command lines to add-before-shl.ll to prepare for D105417. NFC · 2ad2c5d4
  Craig Topper authored Jul 20, 2021
  
  2ad2c5d4
- [RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2) · 98d4adc2
  Craig Topper authored Jul 20, 2021
  98d4adc2
- [RISCV] Use unordered indexed loads for MGATHER. · 84877a09
  Craig Topper authored Jul 20, 2021
  84877a09
- [RISCV] Add test cases to show an issue with our fcvt.wu isel patterns on RV64. · 4f1270a6
  Craig Topper authored Jul 19, 2021
  4f1270a6
Jul 19, 2021
- [SelectionDAG][RISCV] Use isSExtCheaperThanZExt to control whether sext or... · 50302feb
  Craig Topper authored Jul 19, 2021
  50302feb
Jul 18, 2021
- [RISCV] Add more i32 srem/sdiv with power of 2 constant tests. NFC · 00c1cc86
  Craig Topper authored Jul 17, 2021
  00c1cc86
Jul 17, 2021
- [RISCV] Teach computeKnownBitsForTargetNode that VLENB will never be more than 65536/8. · d0f8047d
  Craig Topper authored Jul 17, 2021
  
  d0f8047d
- [RISCV][RVV] Precommit a test case for D105684 · be8159bf
  ShihPo Hung authored Jul 09, 2021
  be8159bf
- [RISCV] Manually emit the best shift for VSCALE lowering to improve codegen. · 173332d1
  Craig Topper authored Jul 17, 2021
  173332d1
Jul 16, 2021
- [RISCV] Rename the fixed vector vwmacc tests to have the 'm' in their filenames. NFC · 2e65ec10
  Craig Topper authored Jul 16, 2021
  
  2e65ec10
- [RISCV] Use tail agnostic policy for fixed vector vwmacc(u). · 8f0343cc
  Craig Topper authored Jul 16, 2021
  8f0343cc
- [RISCV] Teach constant materialization that it can use zext.w at the end with... · 4dbb7880
  Craig Topper authored Jul 16, 2021
  4dbb7880
- Revert "[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID" · e3fa2b1e
  Fraser Cormack authored Jul 16, 2021
  e3fa2b1e
- [RISCV] Lower more BUILD_VECTOR sequences to RVV's VID · a6ca88e9
  Fraser Cormack authored Jun 24, 2021
  a6ca88e9
Jul 14, 2021
- [RISCV] Fix the neutral element in vector 'fadd' reductions · 03a4702c
  Fraser Cormack authored Jul 13, 2021
  03a4702c
Jul 13, 2021
- [RISCV] Use DIVUW/REMUW/DIVW instructions for i8/i16/i32 udiv/urem/sdiv when LHS is constant. · 1e670dc7
  Craig Topper authored Jul 13, 2021
  1e670dc7
- [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions. · 46e89708
  Craig Topper authored Jul 12, 2021
  46e89708
- [RISCV] Support machine constraint "S" · 3d89fb4d
  Fangrui Song authored Jul 13, 2021
  3d89fb4d
- [RISCV] Pass undef VECTOR_SHUFFLE indices on to BUILD_VECTOR · d991b721
  Fraser Cormack authored Jun 23, 2021
  d991b721
Jul 12, 2021
- [SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets. · ec1cdee6
  Eli Friedman authored Jul 12, 2021
  ec1cdee6
Jul 11, 2021
- [RISCV] Add tests for suboptimal handling of negative constants for i32 uaddo/usubo on RV64. NFC · f0393deb
  Craig Topper authored Jul 11, 2021
  f0393deb
- [RISCV] Add tests for suboptimal handling of negative constants on the LHS of... · 6644a611
  Craig Topper authored Jul 11, 2021
  6644a611
- [RISCV] Remove stale FIXME from a test. NFC · 1410aab6
  Craig Topper authored Jul 11, 2021
  1410aab6
- [RISCV] Restore non-constant srem test I accidentally deleted. NFC · 99b8c468
  Craig Topper authored Jul 10, 2021
  
  99b8c468
- [RISCV] Add test cases for div/rem with constant left hand side. NFC · 86109fa9
  Craig Topper authored Jul 10, 2021
  86109fa9
Jul 09, 2021
- [RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD · ed102ce2
  Ben Shi authored Jul 09, 2021
  ed102ce2
Jul 06, 2021
- [RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno · 12d51f95
  Craig Topper authored Jul 06, 2021
  12d51f95
- [RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors. · 2b5e5311
  Craig Topper authored Jul 06, 2021
  2b5e5311
Jun 30, 2021
- CodeGen: Print/parse LLTs in MachineMemOperands · fae05692
  Matt Arsenault authored May 19, 2021
  fae05692
Jun 29, 2021
- [RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being... · 3b6dfa38
  Craig Topper authored Jun 28, 2021
  3b6dfa38
Jun 27, 2021
- [RISCV] Add tests for __builtin_parity idiom. · 4c92e31d
  Craig Topper authored Jun 27, 2021
  4c92e31d
- Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve... · 010f0f00
  Craig Topper authored Jun 27, 2021
  010f0f00
Jun 26, 2021
- [RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions. · 81b2f959
  Craig Topper authored Jun 26, 2021
  
  81b2f959
- [RISCV] Add DAG combine to detect opportunities to replace (i64 (any_extend... · d4f4a1ba
  Craig Topper authored Jun 25, 2021
  d4f4a1ba
Jun 25, 2021
- [RISCV] Permit larger RVV stacks and stack offsets · ab1bd255
  Fraser Cormack authored Jun 22, 2021
  ab1bd255
Jun 24, 2021
- [RISCV] Lower RVV vector SELECTs to VSELECTs · a4729f7f
  Fraser Cormack authored Jun 23, 2021
  a4729f7f
- [CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt. · 91319534
  Craig Topper authored Jun 23, 2021
  91319534
Jun 23, 2021
- [Verifier] Fail on overrunning and invalid indices for {insert,extract} vector intrinsics · 3c4dbf6e
  Joe Ellis authored Jun 18, 2021
  3c4dbf6e