Commits · d3738a09fb2587f584cec5faefda1f37743524a5 · Roger Ferrer / llvm-epi · GitLab

Jul 21, 2021
- [RISCV][test] Add tests for mul optimization in the zba extension with SH*ADD · d3738a09
  Ben Shi authored Jul 21, 2021
  d3738a09
- [MachineVerifier] Diagnose invalid INSERT_SUBREGs · be873832
  Jon Roelofs authored Jul 13, 2021
  be873832
- [GlobalISel] Tail call memcpy/memmove/memset even in the presence of copies · a14b4e34
  Jon Roelofs authored Jul 06, 2021
  a14b4e34
- [GlobalISel] Mark memcpy/memmove/memset as thisreturn · afaf9282
  Jon Roelofs authored Jul 02, 2021
  afaf9282
- [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins · 2fd15202
  Albion Fung authored Jul 20, 2021
  2fd15202
- [tests] Move new tests into the PowerPC folder · f6769b66
  Jon Roelofs authored Jul 20, 2021
  f6769b66
- [AArch64][GlobalISel] Legalize ctpop for v2s64, v2s32, v4s32, v4s16, v8s16 · 75187aa3
  Jon Roelofs authored Jul 20, 2021
  75187aa3
Jul 20, 2021
- [AArch64] Add tests for 128-bit atomic loads with casp available. · c4e1acf1
  Eli Friedman authored Jul 20, 2021
  c4e1acf1
- [PowerPC] Store, load, move from and to registers related builtins · 3434ac9e
  Albion Fung authored Jul 20, 2021
  3434ac9e
- [AArch64][GlobalISel] Select llvm.aarch64.neon.st2 intrinsics · 8f54ebd5
  Jessica Paquette authored Jul 19, 2021
  8f54ebd5
- [AArch64] Use the CMP_SWAP_128 variants added in 843c6140 . · 664a1fd9
  Eli Friedman authored Jul 20, 2021
  664a1fd9
- [IR] Rename `comdat noduplicates` to `comdat nodeduplicate` · 39248779
  Fangrui Song authored Jul 20, 2021
  39248779
- [AArch64] Fix i128 cmpxchg using ldxp/stxp. · 843c6140
  Eli Friedman authored Jul 20, 2021
  843c6140
- [PowerPC] Extra test case for LDARX · 2a7711f3
  Albion Fung authored Jul 20, 2021
  2a7711f3
- [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility · 1a762f93
  Victor Huang authored Jul 20, 2021
  1a762f93
- [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace... · 81efb825
  Craig Topper authored Jul 20, 2021
  81efb825
- [RISCV] Add -mattr=+c command lines to add-before-shl.ll to prepare for D105417. NFC · 2ad2c5d4
  Craig Topper authored Jul 20, 2021
  
  2ad2c5d4
- [PowerPC] Semachecking for XL compat builtin icbt · 59d2ba2a
  Quinn Pham authored Jul 20, 2021
  59d2ba2a
- [RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2) · 98d4adc2
  Craig Topper authored Jul 20, 2021
  98d4adc2
- [PowerPC] Inefficient register allocation of ACC registers results in many copies. · 1a6dc92b
  Stefan Pintilie authored Jul 12, 2021
  1a6dc92b
- [RISCV] Use unordered indexed loads for MGATHER. · 84877a09
  Craig Topper authored Jul 20, 2021
  84877a09
- [AArch64][SVE] Move instcombine like transforms out of SVEIntrinsicOpts · 191f9fa5
  Bradley Smith authored Jul 13, 2021
  191f9fa5
- [AArch64] Regenerate some tests checks. NFC · ee072e20
  David Green authored Jul 20, 2021
  
  ee072e20
- [MIPS][MSA] Regenerate basic operations test checks · e7accb75
  Simon Pilgrim authored Jul 20, 2021
  e7accb75
- [AMDGPU] Improve register computation for indirect calls · 2b08f6af
  Sebastian Neubauer authored Jul 19, 2021
  2b08f6af
- [AMDGPU] Pre-commit test case for D106284 · 0821c882
  Jay Foad authored Jul 19, 2021
  0821c882
- [PowerPC][NFC] add more cases for lfiwzx/lfiwax · fe8b2619
  Chen Zheng authored Jul 20, 2021
  
  fe8b2619
- [AMDGPU] Disable LDS lowering for GFX shaders · 9dc26366
  Stanislav Mekhanoshin authored Jul 16, 2021
  9dc26366
- [AArch64][GlobalISel] Don't form truncstores in postlegalizer-lowering for s128. · 56a6686e
  Amara Emerson authored Jul 20, 2021
  56a6686e
- [PowerPC] Fallback to base's implementation of shouldExpandAtomicCmpXchgInIR... · e2ee27b2
  Kai Luo authored Jul 20, 2021
  e2ee27b2
- [RISCV] Add test cases to show an issue with our fcvt.wu isel patterns on RV64. · 4f1270a6
  Craig Topper authored Jul 19, 2021
  4f1270a6
- CodeGen: Make MachineOptimizationRemarkEmitterPass a CFG analysis · c9ec807b
  Matt Arsenault authored May 12, 2021
  c9ec807b
- AArch64/GlobalISel: Preserve memory types · 30fa074c
  Matt Arsenault authored Jul 16, 2021
  
  30fa074c
Jul 19, 2021
- [SystemZ] Handle NoRegister in SystemZTargetLowering::emitMemMemWrapper(). · 6c0e6895
  Jonas Paulsson authored Jul 16, 2021
  6c0e6895
- Revert "[llvm][sve] Lowering for VLS truncating stores" because it · fd972bb9
  Amy Huang authored Jul 19, 2021
  fd972bb9
- [GlobalISel] Fix load-or combine moving loads across potential aliasing stores. · 03cdb522
  Amara Emerson authored Jul 18, 2021
  03cdb522
- [SelectionDAG][RISCV] Use isSExtCheaperThanZExt to control whether sext or... · 50302feb
  Craig Topper authored Jul 19, 2021
  50302feb
- GlobalISel: Preserve memory types for implicit sret load/stores · 67d61324
  Matt Arsenault authored Jul 16, 2021
  
  67d61324
- [ARM] Remove PromotedBitwiseVT for NEON types · 5561ad8b
  David Green authored Jul 19, 2021
  5561ad8b
- GlobalISel: Preserve LLT when bitcasting loads and stores · 9236125e
  Matt Arsenault authored Jun 10, 2021
  9236125e