Commits · d3a0a65bf01dccadee38d726b6c4d9813c84a048 · Roger Ferrer / llvm-epi · GitLab

Aug 03, 2021
- Reland: "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes" · d3a0a65b
  Paulo Matos authored Jul 28, 2021
  d3a0a65b
- [RISCV] Teach VSETVLI insertion to merge the unused VSETVLI with the one need... · 7900ee0b
  Jianjian GUAN authored Aug 03, 2021
  7900ee0b
- [RuntimeDyldChecker] Delete comparision of integers of different signs · 0023caf9
  luxufan authored Aug 03, 2021
  
  0023caf9
- [RuntimeDyldChecker] Support offset in decode_operand expr · f4e418ac
  luxufan authored Aug 02, 2021
  f4e418ac
- [GlobalOpt] Fix the assert for stored once non-pointer to global address · 7ce98cf5
  Shimin Cui authored Aug 02, 2021
  7ce98cf5
- [AArch64][SelectionDAG] Support passing/returning scalable vectors with unusual types. · 1f62af63
  Eli Friedman authored Aug 02, 2021
  1f62af63
Aug 02, 2021
- [BasicTTIImpl][LoopUnroll] getUnrollingPreferences(): emit ORE remark when... · 6f6e9a86
  Roman Lebedev authored Aug 03, 2021
  6f6e9a86
- [InstCombine] `vector_reduce_{or,and}(?ext(<n x i1>))` -->... · 4ba3326f
  Roman Lebedev authored Aug 03, 2021
  4ba3326f
- [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress · bd13c8e6
  Jessica Paquette authored Aug 02, 2021
  bd13c8e6
- [InstCombine] `vector_reduce_smax(?ext(<n x i1>))` -->... · 554fc9ad
  Roman Lebedev authored Aug 03, 2021
  554fc9ad
- [InstCombine] `vector_reduce_smin(?ext(<n x i1>))` -->... · f47b7b6d
  Roman Lebedev authored Aug 02, 2021
  f47b7b6d
- Revert "[unroll] Move multiple exit costing into consumer pass [NFC]" · c7770574
  Nikita Popov authored Aug 02, 2021
  c7770574
- [ValueTracking] Fix computeConstantRange to use "may" instead of "always" semantics for llvm.assume · b58eda39
  Chang-Sun Lin, Jr authored Aug 02, 2021
  b58eda39
- [InstCombine] `vector_reduce_umax(?ext(<n x i1>))` --> `?ext(vector_reduce_or(<n x i1>))` (PR51259) · b9b7162b
  Roman Lebedev authored Aug 02, 2021
  b9b7162b
- [InstCombine] `vector_reduce_umin(?ext(<n x i1>))` -->... · 0c137980
  Roman Lebedev authored Aug 02, 2021
  0c137980
- [unroll] Move multiple exit costing into consumer pass [NFC] · 76940577
  Philip Reames authored Aug 02, 2021
  76940577
- [DFAJumpThreading] Use SmallPtrSet for Visited (NFC) · 380b8a60
  Nikita Popov authored Aug 02, 2021
  380b8a60
- [DFAJumpThreading] Use insert return value (NFC) · 3f7aea1a
  Nikita Popov authored Aug 02, 2021
  3f7aea1a
- [DFAJumpThreading] Remove unnecessary includes (NFC) · 84602f98
  Nikita Popov authored Aug 02, 2021
  84602f98
- [DFAJumpThreading] Mark DT as preserved in LegacyPM · e97524cb
  Nikita Popov authored Aug 02, 2021
  e97524cb
- [InstCombine] `vector_reduce_mul(?ext(<n x i1>))` --> `zext(vector_reduce_and(<n x i1>))` (PR51259) · 469793ef
  Roman Lebedev authored Aug 02, 2021
  469793ef
- [unrollruntime] Pull out a helper function for readability and eventual reuse [nfc] · 9016beaa
  Philip Reames authored Aug 02, 2021
  
  9016beaa
- Revert "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes" · 245f2ee6
  Paulo Matos authored Aug 02, 2021
  245f2ee6
- [unroll] Add clarifying comment · ebc4c4e3
  Philip Reames authored Aug 02, 2021
  ebc4c4e3
- [DWARF] Don't process .debug_info relocations for DWO Context · 5a865b0b
  Alexander Yermolovich authored Aug 02, 2021
  5a865b0b
- [WebAssembly] Add new pass to lower int/ptr conversions of reftypes · ce1c59de
  Paulo Matos authored Jul 28, 2021
  ce1c59de
- [VPlan] Use defined and ops VPValues to print VPInterleaveRecipe. · bb725c98
  Florian Hahn authored Aug 02, 2021
  bb725c98
- [InstCombine] `xor` reduction w/ i1 elt type is a parity check · 1e801439
  Roman Lebedev authored Aug 02, 2021
  1e801439
- [WebAssembly] Compute known bits for SIMD bitmask intrinsics · 417e5006
  Thomas Lively authored Aug 02, 2021
  417e5006
- [ARM] Remove setPreservesCFG from ARMBlockPlacement · c423a586
  David Green authored Aug 02, 2021
  c423a586
- [AArch64] Optimise min/max lowering in ISel · b01417d3
  Irina Dobrescu authored Jul 22, 2021
  b01417d3
- [AMDGPU] Disable NSA for BVH instructions when appropriate · 675c9423
  Carl Ritson authored Aug 02, 2021
  675c9423
- [hwasan] Detect use after scope within function. · 66b4aafa
  Florian Mayer authored Aug 02, 2021
  66b4aafa
- [TTI] Add basic SK_InsertSubvector shuffle mask recognition · 7397dcb4
  Simon Pilgrim authored Aug 02, 2021
  7397dcb4
- Fix MSVC signed/unsigned comparison warning. NFCI. · 05790501
  Simon Pilgrim authored Jul 31, 2021
  
  05790501
- [LoopFlatten] Fix missed LoopFlatten opportunity · f117ed54
  Rosie Sumpter authored Jul 30, 2021
  f117ed54
- [ARM] Revert WLSTP to DLSTP if the target block is out of range · 28293918
  David Green authored Aug 02, 2021
  28293918
- [AArch64][AsmParser] NFC: Parser.Lex() -> Lex() · 7ed0120d
  Cullen Rhodes authored Aug 02, 2021
  7ed0120d
- [GC][NFC] Make getGCStrategy by name available in IR · c5b63714
  Max Kazantsev authored Aug 02, 2021
  c5b63714
- [AMDGPU][GlobalISel] Add missing default mapping for BVH intrinsics · a441de6d
  Carl Ritson authored Aug 02, 2021
  a441de6d