Show failure to simplify cases with zero op/flags

llvm-svn: 352196

If a stack trace or similar has a list of addresses from an executable
or DSO loaded at a variable address (e.g. due to ASLR), the addresses
will not directly correspond to the addresses stored in the object file.
If a user wishes to use llvm-symbolizer, they have to subtract the load
address from every address. This is somewhat inconvenient, especially as
the output of --print-address will result in the adjusted address being
listed, rather than the address coming from the stack trace, making it
harder to map results between the two.

This change adds a new switch to llvm-symbolizer --adjust-vma which
takes an offset, which is then used to automatically do this
calculation. The printed address remains the input address (allowing for
easy mapping), whilst the specified offset is applied to the addresses
when performing the lookup.

The switch is conceptually similar to llvm-objdump's new switch of the
same name (see D57051), which in turn mirrors a GNU switch. There is no
equivalent switch in addr2line.

Reviewed by: grimar

Differential Revision: https://reviews.llvm.org/D57151

llvm-svn: 352195

llvm-svn: 352194

llvm-svn: 352193

llvm-svn: 352191

llvm-svn: 352190

Same as ARM.

On this occasion we split some of the instruction select tests for more
complicated instructions into their own files, so we can reuse them for
ARM and Thumb mode. Likewise for the legalizer tests.

llvm-svn: 352188

r351882 introduced some superfluous calls to mark G_INTTOPTR and
G_PTRTOINT as legal (looks like a rebase mishap). Remove them.

llvm-svn: 352187

This patch extends TableGen language with !cond operator.
Instead of embedding !if inside !if which can get cumbersome,
one can now use !cond.
Below is an example to convert an integer 'x' into a string:

    !cond(!lt(x,0) : "Negative",
          !eq(x,0) : "Zero",
          !eq(x,1) : "One,
          1        : "MoreThanOne")

Reviewed By: hfinkel, simon_tatham, greened
Differential Revision: https://reviews.llvm.org/D55758

llvm-svn: 352185

This change adds an option -g to llvm-objcopy which is an alias for the existing option --strip-debug.

This fixes PR40003.

Reviewed by: alexshap

Differential Revision: https://reviews.llvm.org/D57217

llvm-svn: 352182

Match the coverage of test\CodeGen\X86\avx512-shuffle-schedule.ll so we can get rid of -print-schedule (and fix PR37160) without losing schedule tests

llvm-svn: 352179

Align checks for absolute addressing mode with its current
implementation (SR is used as a base register).

This fixes https://bugs.llvm.org/show_bug.cgi?id=39993

Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D56785

llvm-svn: 352178

llvm-svn: 352176

Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support.

We'd use VSX float comparison instruction instead of non-vsx float comparison instruction 
if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and 
VSFRC correspondingly if VSX feature is opened.

If the target does not have corresponding VSX instruction comparison for some type, 
just copy VSX-related register to common float register class and use non-vsx comparison instruction.

Differential Revision: https://reviews.llvm.org/D57078

llvm-svn: 352174

[X86] Add non-masked versions of vpconflict intrinsics so we can use a select in the header file in clang.

I'll remove and autoupgrade the old intrinsics in a future commit.

llvm-svn: 352172

Follow the same custom legalisation strategy as used in D57085 for
variable-length shifts (see that patch summary for more discussion). Although
we may lose out on some late-stage DAG combines, I think this custom
legalisation strategy is ultimately easier to reason about.

There are some codegen changes in rv64m-exhaustive-w-insts.ll but they are all
neutral in terms of the number of instructions.

Differential Revision: https://reviews.llvm.org/D57096

llvm-svn: 352171

2nd part of D57095 with the same reason, just in another place. We never
fold branches that are not immediately in the current loop, but this check
is missing in `IsEdgeLive` As result, it may think that the edge in subloop is
dead while it's live. It's a pessimization in the current stance.

Differential Revision: https://reviews.llvm.org/D57147
Reviewed By: rupprecht	

llvm-svn: 352170

The previous DAG combiner-based approach had an issue with infinite loops
between the target-dependent and target-independent combiner logic (see
PR40333). Although this was worked around in rL351806, the combiner-based
approach is still potentially brittle and can fail to select the 32-bit shift
variant when profitable to do so, as demonstrated in the pr40333.ll test case.

This patch instead introduces target-specific SelectionDAG nodes for
SHLW/SRLW/SRAW and custom-lowers variable i32 shifts to them. pr40333.ll is a
good example of how this approach can improve codegen.

This adds DAG combine that does SimplifyDemandedBits on the operands (only
lower 32-bits of first operand and lower 5 bits of second operand are read).
This seems better than implementing SimplifyDemandedBitsForTargetNode as there
is no guarantee that would be called (and it's not for e.g. the anyext return
test cases). Also implements ComputeNumSignBitsForTargetNode.

There are codegen changes in atomic-rmw.ll and atomic-cmpxchg.ll but the new
instruction sequences are semantically equivalent.

Differential Revision: https://reviews.llvm.org/D57085

llvm-svn: 352169

Also move G_GEP actions together.

llvm-svn: 352168

llvm-svn: 352167

llvm-svn: 352166

llvm-svn: 352165

llvm-svn: 352162

llvm-svn: 352161

While a cold invoke itself and its unwind destination can't be
extracted, code which unconditionally executes before/after the invoke
may still be profitable to extract.

With cost model changes from D57125 applied, this gives a 3.5% increase
in split text across LNT+externals on arm64 at -Os.

llvm-svn: 352160

Also legalize 64-bit compares for AMDGPU

llvm-svn: 352157

llvm-svn: 352155

Otherwise they are treated as dynamic allocas, which ends up increasing
code size significantly. This reduces size of Chromium base_unittests
by 2MB (6.7%).

Differential Revision: https://reviews.llvm.org/D57205

llvm-svn: 352152

Differential Revision: https://reviews.llvm.org/D57202

llvm-svn: 352146

llvm-svn: 352143

Reviewers: pcc, rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D57192

llvm-svn: 352142

- gcc doesn't understand -Wstring-conversion, so pass that only to clang
- disable a few gcc warnings that are noisy and also disabled in the cmake build
- -Wstrict-aliasing pointed out that the cmake build builds clang with
  -fno-strict-aliasing, so do that too

Differential Revision: https://reviews.llvm.org/D57191

llvm-svn: 352141

See the bot error message reported in https://reviews.llvm.org/D57082.

Avoid trying to match full class names in -debug-pass-manager output,
because they aren't portable.

llvm-svn: 352138

llvm-svn: 352136

llvm-svn: 352133

This patch exploits the instructions that store a single element from a vector
to preform a (store (extract_elt)). We already have code that does this with
ISA 3.0 instructions that were added to handle i8/i16 types. However, we had
never exploited the existing ones that handle f32/f64/i32/i64 types.

Differential revision: https://reviews.llvm.org/D56175

llvm-svn: 352131

llvm-svn: 352130

llvm-svn: 352129

llvm-svn: 352128

As noted in D57156, we want to check at least part of
this pattern earlier (in combining), so this will allow
the code to be shared instead of duplicated.

llvm-svn: 352127