Commits · d503940e8f33ed7919a20bcdb87e1a067f175abe · Roger Ferrer / llvm-epi · GitLab

Oct 31, 2016
- [PPC] add absolute difference altivec instructions and matching intrinsics · 60bdfe5a
  Nemanja Ivanovic authored Oct 31, 2016
  60bdfe5a
- GlobalISel: allow truncating pointer casts on AArch64. · 037af52c
  Tim Northover authored Oct 31, 2016
  037af52c
- GlobalISel: translate stack protector intrinsics · cdf23f1d
  Tim Northover authored Oct 31, 2016
  cdf23f1d
- [x86][inline-asm][AVX512][llvm][PART-2] · 68a5c536
  Michael Zuckerman authored Oct 31, 2016
  68a5c536
- [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. · 54bfd548
  Artem Tamazov authored Oct 31, 2016
  54bfd548
- [Hexagon] Don't expand mux instructions with both sources identical · 22586dcb
  Krzysztof Parzyszek authored Oct 31, 2016
  22586dcb
- [SystemZ] Rework processor feature definitions and add -mcpu=archX support · 2e5e51b3
  Ulrich Weigand authored Oct 31, 2016
  2e5e51b3
- [SystemZ] Guard LEFR/LFER with FeatureVector · d28be373
  Ulrich Weigand authored Oct 31, 2016
  d28be373
- [SystemZ] Correctly diagnose missing features in AsmParser · d9001301
  Ulrich Weigand authored Oct 31, 2016
  d9001301
- [SystemZ] Fix encoding of MVCK and .insn ss · ec5d779e
  Ulrich Weigand authored Oct 31, 2016
  ec5d779e
- [SystemZ] Model 2 VBU units (not 1) in SystemZScheduleZ13.td. · 6788ddea
  Jonas Paulsson authored Oct 31, 2016
  6788ddea
- Improved cost model for FDIV and FSQRT, by Andrew Tischenko · d07c731d
  Alexey Bataev authored Oct 31, 2016
  d07c731d
- [AVX-512] Add missing patterns for selecting masked vector extracts that started from shuffles. · d4e58070
  Craig Topper authored Oct 31, 2016
  d4e58070
Oct 30, 2016
- [X86] Use intrinsics table for PMADDUBSW and PMADDWD so that we can use the... · b7781a95
  Craig Topper authored Oct 30, 2016
  b7781a95
- [X86] Don't use loadv2i64 on SSE version of PMULHRSW. Use memopv2i64 instead. · bf9e5a16
  Craig Topper authored Oct 30, 2016
  bf9e5a16
Oct 29, 2016
- [X86] Use intrinsics table for VPMULHRSW intrincis so that the legacy... · defe9ffb
  Craig Topper authored Oct 29, 2016
  defe9ffb
- Fixed FMA + FNEG combine. · 519b4ccd
  Elena Demikhovsky authored Oct 29, 2016
  519b4ccd
- AMDGPU: Use 1/2pi inline imm on VI · c88ba36e
  Matt Arsenault authored Oct 29, 2016
  c88ba36e
- AArch64DeadRegisterDefinitionsPass: Cleanup; NFC · 7d78614a
  Matthias Braun authored Oct 29, 2016
  7d78614a
- AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructions · 6695ba04
  Tom Stellard authored Oct 28, 2016
  6695ba04
- AMDGPU: Fix instruction flags for s_endpgm · 4e9c1e3a
  Matt Arsenault authored Oct 28, 2016
  4e9c1e3a
Oct 28, 2016
- AMDGPU: Add definitions for scalar store instructions · 7b647556
  Matt Arsenault authored Oct 28, 2016
  7b647556
- AMDGPU: Rename glc operand type · 4b6a6cc8
  Matt Arsenault authored Oct 28, 2016
  4b6a6cc8
- [NVPTX] Compute 'rem' using the result of 'div', if possible. · f0a80ba3
  Justin Lebar authored Oct 28, 2016
  f0a80ba3
- AMDGPU: Diagnose using too many SGPRs · 4eae3019
  Matt Arsenault authored Oct 28, 2016
  4eae3019
- AMDGPU: Fix using incorrect private resource with no allocation · 08906a3c
  Matt Arsenault authored Oct 28, 2016
  08906a3c
- Implement vector count leading/trailing bytes with zero lsb and vector parity · e28a0fc7
  Nemanja Ivanovic authored Oct 28, 2016
  e28a0fc7
- [Hexagon] Maintain kill flags through splitting in expand-condsets · 87a47be0
  Krzysztof Parzyszek authored Oct 28, 2016
  87a47be0
- AMDGPU/SI: Handle hazard with s_rfe_b64 · aea899e2
  Tom Stellard authored Oct 27, 2016
  aea899e2
- AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}lane · 04051b5f
  Tom Stellard authored Oct 27, 2016
  04051b5f
- AMDGPU/SI: Fix unused variable warning on non-debug builds · 6b9c1be4
  Tom Stellard authored Oct 27, 2016
  6b9c1be4
- AMDGPU/SI: Handle hazard with > 8 byte VMEM stores · b133fbb9
  Tom Stellard authored Oct 27, 2016
  b133fbb9
Oct 27, 2016
- AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer · 30d30824
  Tom Stellard authored Oct 27, 2016
  30d30824
- [X86][AVX512] Fix MUL v8i64 costs on non-AVX512DQ targets · d23219b9
  Simon Pilgrim authored Oct 27, 2016
  d23219b9
- [X86][AVX512DQ] Move v2i64 and v4i64 MUL lowering to tablegen · 47c1ff7a
  Simon Pilgrim authored Oct 27, 2016
  47c1ff7a
- ARM: ensure that the Windows DBZ check is in range · 075d2e3c
  Saleem Abdulrasool authored Oct 27, 2016
  075d2e3c
- [mips] Do not allow -opt-bisect-limit to skip the PIC call optimization pass. · cfb005a0
  Vasileios Kalintiris authored Oct 27, 2016
  cfb005a0
- [X86][AVX512DQ] Improve lowering of MUL v2i64 and v4i64 · 820e1326
  Simon Pilgrim authored Oct 27, 2016
  820e1326
- [Hexagon] Do not expand ISD::SELECT for HVX vectors · 046da746
  Krzysztof Parzyszek authored Oct 27, 2016
  046da746
- [ARM] Predicate UMAAL selection on hasDSP. · e7d9505c
  Sam Parker authored Oct 27, 2016
  e7d9505c