Commits · d5659808b2fabadd2fff4f19d7aed2e2ff3435f5 · Roger Ferrer / llvm-epi · GitLab

Jun 19, 2023
- [AIX][TLS] Generate 64-bit local-exec access code sequence · d5659808
  Amy Kwan authored Jun 17, 2023
  d5659808
- Recommit "[LSR] Consider post-inc form when creating extends/truncates." · dae5cd73
  Florian Hahn authored Jun 19, 2023
  dae5cd73
- [AMDGPU] Add basic support for extended i8 perm matching · ac2d6df2
  Jeffrey Byrnes authored May 08, 2023
  ac2d6df2
- [AMDGPU] Reimplement the GFX11 early release VGPRs optimization · eb749176
  Jay Foad authored Jun 19, 2023
  eb749176
- AMDGPU: Remove amdgpu-waves-per-eu support in old attribute pass · 7c895811
  Matt Arsenault authored Dec 10, 2021
  7c895811
- [Hexagon] Fix range checks for immediate operands · 734881a6
  Krzysztof Parzyszek authored Jun 19, 2023
  734881a6
- [AArch64] Add and expand the testing of fmin/fmax reduction. NFC · d0f56c3e
  David Green authored Jun 19, 2023
  d0f56c3e
- [AArch64] More tablegen patterns for addp of two extracts · 16b46dde
  David Green authored Jun 19, 2023
  16b46dde
- [AArch64] Add tablegen patterns for faddp of two extracts · 68f34e4d
  David Green authored Jun 19, 2023
  68f34e4d
- [XRay] Mark Mach-O xray_instr_map and xray_fn_idx as S_ATTR_LIVE_SUPPORT · b9a134aa
  Fangrui Song authored Jun 18, 2023
  b9a134aa
- [RISCV] Match shl (ext v, splat 1) to vector widening add. · 04ed822d
  Jianjian GUAN authored Jun 16, 2023
  04ed822d
Jun 18, 2023
- [XRay][test] Make tests less sensitive to .Ltmp/Ltmp label changes · 49b61ead
  Fangrui Song authored Jun 18, 2023
  
  49b61ead
- [GlobalIsel][X86] selectDivRem - fix typo in 64-bit AH handling code · fb60dda1
  Simon Pilgrim authored Jun 18, 2023
  fb60dda1
- [GlobalIsel][X86] Regenerate srem/urem select test coverage · 46479ea7
  Simon Pilgrim authored Jun 18, 2023
  
  46479ea7
- [CodeGenPrepare][RISCV] Remove asserting VH references before erasing the dead GEP · 315e3001
  Yingwei Zheng authored Jun 18, 2023
  315e3001
- [X86] Regenerate tls.ll and reuse common linux check prefixes · e1164c7a
  Simon Pilgrim authored Jun 18, 2023
  
  e1164c7a
- [X86] Regenerate add32ri8.ll · d7464ea5
  Simon Pilgrim authored Jun 18, 2023
  
  d7464ea5
- [Hexagon] Add missing patterns for boolean [v]selects · 5ad9adb9
  Krzysztof Parzyszek authored Jun 17, 2023
  5ad9adb9
- [Hexagon] Handle all compares of i1 and vNi1 · 833438ee
  Krzysztof Parzyszek authored Jun 17, 2023
  833438ee
- [Hexagon] Add missing patterns for truncate to vNi1 · d1c3ec61
  Krzysztof Parzyszek authored Jun 17, 2023
  
  d1c3ec61
Jun 17, 2023
- Revert "[LSR] Consider post-inc form when creating extends/truncates." · 1797ab36
  Florian Hahn authored Jun 17, 2023
  1797ab36
- [AMDGPU] Update test after abfeda5a . · fe19036e
  Florian Hahn authored Jun 17, 2023
  
  fe19036e
- [AMDGPU] Generate checks for load-constant tests · 01b51288
  Jay Foad authored Jun 16, 2023
  01b51288
- [LoongArch] Fix handling of the chain of CSRWR and CSRXCHG nodes · c216ce0e
  Weining Lu authored Jun 17, 2023
  c216ce0e
- [LoongArch][NFC] Precommit test for D153120 (the fix of CSRWR and CSRXCHG) · 4a69fd62
  Weining Lu authored Jun 17, 2023
  4a69fd62
- [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt) · 12fee611
  LiaoChunyu authored Jun 17, 2023
  12fee611
- [RISCV] Make all vector binops use the _TU pseudo form · 95697def
  Philip Reames authored Jun 16, 2023
  95697def
- [RISCV] Introduce RISCVISD::VWMACC(U/SU)_VL opcode · a986998b
  Nitin John Raj authored Jun 14, 2023
  a986998b
- [Hexagon] Generate correct instruction for store i1, ($Rs<<$u2 + $Rt) · 77e4c48e
  Krzysztof Parzyszek authored Jun 16, 2023
  77e4c48e
- Revert "AMDGPU: Drop and auto-upgrade llvm.amdgcn.ldexp to llvm.ldexp" · d9333e36
  Matt Arsenault authored Jun 16, 2023
  d9333e36
- AMDGPU: Drop and auto-upgrade llvm.amdgcn.ldexp to llvm.ldexp · 1159c670
  Matt Arsenault authored Apr 28, 2023
  
  1159c670
Jun 16, 2023
- [Hexagon] Properly combine overlapping stores in HVC · 4351060a
  Krzysztof Parzyszek authored Jun 16, 2023
  
  4351060a
- AMDGPU: Propagate amdgpu-waves-per-eu with attributor · b9c6d9e6
  Matt Arsenault authored Sep 13, 2021
  b9c6d9e6
- [RISCV] Treat __riscv_vsetvl_*(-1) as vlmax. · 8a403166
  Craig Topper authored Jun 16, 2023
  8a403166
- [AArch64] Try to convert vector shift operation into vector add operation · 82d330e0
  Jingu Kang authored Jun 15, 2023
  82d330e0
- [NFC] Autogenerate CodeGen/ARM/vlddup.ll · c8f4ba37
  Amaury Séchet authored Jun 16, 2023
  
  c8f4ba37
- [NFC] Autogenerate CodeGen/ARM/sub-cmp-peephole.ll · ec77747f
  Amaury Séchet authored Jun 16, 2023
  
  ec77747f
- [AMDGPU] Regenerate llvm.amdgcn.s.buffer.load checks · 21247595
  Jay Foad authored Jun 16, 2023
  
  21247595
- [GlobalISel][X86] Add handling of scalar G_UADDO/G_USUBO opcodes · 0342aefa
  Simon Pilgrim authored Jun 16, 2023
  0342aefa
- [GlobalISel][X86] Add handling of scalar G_USUBE opcodes · 91afb4b7
  Simon Pilgrim authored Jun 16, 2023
  91afb4b7