Commits · d61996473dd9481da9ffc40cea608a5e6eaacf06 · Roger Ferrer / llvm-epi · GitLab

Oct 23, 2020
- AMDGPU: Increase branch size estimate with offset bug · d6199647
  Matt Arsenault authored Oct 22, 2020
  d6199647
- [LSR] ignore profitable chain when reg num is not major cost. · 1e0b6c1d
  Chen Zheng authored Oct 20, 2020
  1e0b6c1d
- [X86] lowerShuffleWithPERMV - use MVT::changeTypeToInteger helper. NFCI. · 936ef89e
  Simon Pilgrim authored Oct 23, 2020
  
  936ef89e
- [ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC · cb86522c
  Evgeny Leviant authored Oct 23, 2020
  cb86522c
- [AArch64] Implement getIntrinsicInstrCost, handle min/max intrinsics. · 0fcc6f7a
  Florian Hahn authored Oct 23, 2020
  0fcc6f7a
- [AMDGPU] Add simplification/combines for llvm.amdgcn.fmul.legacy · 86a480e9
  Jay Foad authored Oct 06, 2020
  86a480e9
- [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate · 7a78073b
  Evgeny Leviant authored Oct 23, 2020
  7a78073b
- [AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering · 19dc9c97
  Jessica Paquette authored Oct 20, 2020
  19dc9c97
Oct 22, 2020
- [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 · 147b9497
  Jessica Paquette authored Oct 19, 2020
  147b9497
- [AMDGPU] Add amdgpu specific loop threshold metadata · 3c1273d7
  Tim Corringham authored Jul 28, 2020
  3c1273d7
- [NFC][MC] Use MCRegister for ReachingDefAnalysis APIs · e24537d4
  Mircea Trofin authored Oct 21, 2020
  e24537d4
- [AMDGPU] Fix expansion of i16 MULH · 7ae0033c
  Piotr Sobczak authored Oct 22, 2020
  7ae0033c
- [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate · ed6a91f4
  Evgeny Leviant authored Oct 22, 2020
  ed6a91f4
- [X86] X86AsmParser - make methods const where possible. NFCI. · 26929780
  Simon Pilgrim authored Oct 22, 2020
  26929780
- [X86] Return const& in IntelExprStateMachine::getIdentifierInfo(). NFCI. · 091b18ba
  Simon Pilgrim authored Oct 22, 2020
  091b18ba
- AMDGPU: Fix not always reserving VGPRs used for SGPR spilling · d5c05616
  Matt Arsenault authored Oct 15, 2020
  d5c05616
- AMDGPU: Implement getNoPreservedMask · d3bcfe2a
  Matt Arsenault authored Oct 15, 2020
  d3bcfe2a
- [CodeGen] Split MVT::changeTypeToInteger() functionality from EVT::changeTypeToInteger(). · 794dc7ad
  Simon Pilgrim authored Oct 22, 2020
  794dc7ad
- [DebugInstrRef] Substitute debug value numbers to handle optimizations · d7327599
  Jeremy Morse authored Oct 22, 2020
  d7327599
- [X86] Add User Interrupts(UINTR) instructions · be39a6fe
  Tianqing Wang authored Oct 22, 2020
  be39a6fe
- [NFC][AMDGPU] Reorder SIMemoryLegalizer functions to be consistent · 8e8cc587
  Tony authored Oct 21, 2020
  8e8cc587
- [X86] Support customizing stack protector guard · 7c3fea77
  Xiang1 Zhang authored Oct 22, 2020
  7c3fea77
- [FPEnv][X86][SystemZ] Use different algorithms for i64->double uint_to_fp... · 9e884169
  Craig Topper authored Oct 21, 2020
  9e884169
- [NFC] Set return type of getStackPointerRegisterToSaveRestore to Register · 4634ad6c
  Gaurav Jain authored Oct 21, 2020
  4634ad6c
Oct 21, 2020
- [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate · bf9edcb6
  Evgeny Leviant authored Oct 21, 2020
  bf9edcb6
- [AMDGPU] Fixed v_swap_b32 match · 611959f0
  Stanislav Mekhanoshin authored Oct 16, 2020
  611959f0
- [AMDGPU] Refactor SOPC & SOPP .td for extension · f6d7832f
  Joe Nash authored Oct 19, 2020
  f6d7832f
- AMDGPU: Lower the threshold reported for maximum stack size exceeded · 1ed4caff
  Matt Arsenault authored Oct 16, 2020
  1ed4caff
- AMDGPU: Propagate amdgpu-flat-work-group-size attributes · 53c43431
  Matt Arsenault authored Oct 19, 2020
  53c43431
- [ARM] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans · dfd6b69e
  Paul C. Anagnostopoulos authored Oct 20, 2020
  dfd6b69e
- [SystemZ] Mark unsaved argument R6 as live throughout function. · 1606755d
  Jonas Paulsson authored Oct 15, 2020
  1606755d
- Add "SkipDead" parameter to TargetInstrInfo::DefinesPredicate · 9a2d2bed
  Nicholas Guy authored Sep 28, 2020
  9a2d2bed
- [AMDGPU] Fix off by one in assert · 5290f50e
  Sebastian Neubauer authored Oct 20, 2020
  5290f50e
- [AMDGPU][TableGen] Make more use of !ne !not !and !or. NFC. · f6a5699c
  Jay Foad authored Oct 21, 2020
  
  f6a5699c
- [X86] Remove period from end of error message in assembler · d4d0b41a
  Craig Topper authored Oct 21, 2020
  d4d0b41a
- [X86] Error on using h-registers with REX prefix in the assembler instead of... · 79a69f55
  Craig Topper authored Oct 20, 2020
  79a69f55
- [AMDGPU][NFC] Fix missing size in comment · 324a15ce
  Carl Ritson authored Oct 21, 2020
  
  324a15ce
- [AMDGPU] Avoid inserting noops during scheduling · ebdcef20
  Austin Kerbow authored Oct 19, 2020
  ebdcef20
- [HazardRec] Allow inserting multiple wait-states simultaneously · 37d90789
  Austin Kerbow authored Oct 19, 2020
  37d90789
- [AMDGPU] Optimize waitcnt insertion for flat memory operations · 1bc7bfff
  Tony authored Oct 16, 2020
  1bc7bfff