Commits · d625bedb405b32e669566c1a2eceeddfc2ba2f5e · Roger Ferrer / llvm-epi · GitLab

May 16, 2017
- Revert "[ARM] Mark LEApcrel instructions as isAsCheapAsAMove" · d69570e0
  Renato Golin authored May 16, 2017
  d69570e0
- [X86] Replace slow LEA instructions in X86 · 52e89257
  Lama Saba authored May 16, 2017
  52e89257
- [GlobalISel][X86] Split memop test file. NFC · 3a455044
  Igor Breger authored May 16, 2017
  3a455044
- [ShrinkWrapping] Handle restores on no-return paths · ebbc7159
  Francis Visoiu Mistrih authored May 15, 2017
  ebbc7159
May 15, 2017
- AArch64: use linker-private symbols for globals in MachO. · 203c6f05
  Tim Northover authored May 15, 2017
  203c6f05
- Revert r302678 "[AArch64] Enable use of reduction intrinsics." · bd6e9e77
  Hans Wennborg authored May 15, 2017
  bd6e9e77
- CodeGen: BlockPlacement: Increase tail duplication size for O3. · 7d531dae
  Kyle Butt authored May 15, 2017
  7d531dae
- [NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146) · 55ff5786
  Simon Pilgrim authored May 15, 2017
  55ff5786
- [AArch64] Enable FeatureFuseAES on Cortex-A72. · af91e7e6
  Florian Hahn authored May 15, 2017
  af91e7e6
- [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64 · 167f8b69
  Dmitry Preobrazhensky authored May 15, 2017
  167f8b69
- Test commit. · aa2b7a6f
  Dinar Temirbulatov authored May 15, 2017
  aa2b7a6f
- [ARM] Mark LEApcrel instructions as isAsCheapAsAMove · 9486becf
  John Brawn authored May 15, 2017
  9486becf
- [ARM] Mark LEApcrel as not having side effects · 43132c46
  John Brawn authored May 15, 2017
  43132c46
- [X86] Relocate code of replacement of subtarget unsupported masked memory... · c5490e5a
  Ayman Musa authored May 15, 2017
  c5490e5a
- [GlobalISel][X86] G_BR instruction select test · 06c61e86
  Igor Breger authored May 15, 2017
  06c61e86
May 14, 2017
- [X86] Add avx512vl command lines to the 128/256-bit vector-lzcnt tests so we... · c27dc9f7
  Craig Topper authored May 14, 2017
  c27dc9f7
- [X86] Cleanup some of the check-prefixes in the vector-lzcnt tests. · 87804dfe
  Craig Topper authored May 14, 2017
  87804dfe
- [X86][AVX] Allow 32-bit targets to peek through subvectors to extract constant... · f3ee9c69
  Simon Pilgrim authored May 14, 2017
  f3ee9c69
- [X86][AVX] Add additional 32-bit target vector shift tests · f3e87ac5
  Simon Pilgrim authored May 14, 2017
  f3e87ac5
- [SelectionDAG] Added support for EXTRACT_SUBVECTOR/CONCAT_VECTORS demandedelts... · 754c1618
  Simon Pilgrim authored May 13, 2017
  754c1618
May 13, 2017
- [X86][SSE] Test showing missing EXTRACT_SUBVECTOR/CONCAT_VECTORS demandedelts... · 78b0ce03
  Simon Pilgrim authored May 13, 2017
  78b0ce03
- [SelectionDAG] Add VECTOR_SHUFFLE support to ComputeNumSignBits · 7666afd0
  Simon Pilgrim authored May 13, 2017
  7666afd0
- [X86][SSE] Test showing inability of ComputeNumSignBits to resolve shuffles · ded23a7f
  Simon Pilgrim authored May 13, 2017
  ded23a7f
- [x86, SSE] AVX1 PR28129 (256-bit all-ones rematerialization) · ef46c276
  Simon Pilgrim authored May 13, 2017
  ef46c276
- [AVR] When lowering Select8/Select16, put newly generated MBBs in the same spot · 0c4debc1
  Dylan McKay authored May 13, 2017
  0c4debc1
May 12, 2017
- [x86] add vector tests for demanded bits; NFC · 1b858940
  Sanjay Patel authored May 12, 2017
  1b858940
- AMDGPU/SI: Don't promote to vector if the load/store is volatile. · 161e8c39
  Changpeng Fang authored May 12, 2017
  161e8c39
- [NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146) · a1978aae
  Simon Pilgrim authored May 12, 2017
  a1978aae
- Add LiveRangeShrink pass to shrink live range within BB. · 65dd23e2
  Dehao Chen authored May 12, 2017
  65dd23e2
- AMDGPU: Add lit.local.cfg to disable global-isel tests when global-isel is disabled · fab6b1af
  Tom Stellard authored May 12, 2017
  fab6b1af
- AMDGPU/GlobalISel: Mark 32-bit integer constants as legal · a0d67c74
  Tom Stellard authored May 12, 2017
  a0d67c74
- [SPARC] Support 'f' and 'e' inline asm constraints. · d4e1b00e
  James Y Knight authored May 12, 2017
  d4e1b00e
- [x86] add tests for potential vector narrowing optimization (PR32790) · ae362303
  Sanjay Patel authored May 12, 2017
  ae362303
- Handle a COPY with undef source operand in LowerCopy() · d1ec7385
  Jonas Paulsson authored May 12, 2017
  d1ec7385
- [IfConversion] Keep the CFG updated incrementally in IfConvertTriangle · ce3ec451
  Mikael Holmen authored May 12, 2017
  ce3ec451
- [PPC] Change the register constraint of the first source operand of... · 22e7da95
  Guozhi Wei authored May 11, 2017
  22e7da95
May 11, 2017
- [AArch64][MachineCombine] Fold FNMUL+FSUB -> FNMADD. · aeffffdb
  Chad Rosier authored May 11, 2017
  aeffffdb
- [MSP430] Generate EABI-compliant libcalls · 38e30197
  Vadzim Dambrouski authored May 11, 2017
  38e30197
- AMDGPU: Remove tfe bit from flat instruction definitions · 47ccafe7
  Matt Arsenault authored May 11, 2017
  47ccafe7
- AMDGPU: Pull fneg out of extract_vector_elt · bf5482e4
  Matt Arsenault authored May 11, 2017
  bf5482e4