Commits · d63d662d3cc51219fb08908ebea8d5851e53adb8 · Roger Ferrer / llvm-epi · GitLab

May 26, 2021
- [RISCV] Remove --riscv-no-aliases from RVV tests · d63d662d
  Jessica Clarke authored May 26, 2021
  d63d662d
- [RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI pass. · b2c7ac87
  Craig Topper authored May 26, 2021
  b2c7ac87
- [RISCV] Enable cross basic block aware vsetvli insertion · 1b47a3de
  Craig Topper authored May 25, 2021
  1b47a3de
- [RISCV] Pre-commit fixed-length mask vselect tests · 7e27e427
  Fraser Cormack authored May 26, 2021
  7e27e427
May 25, 2021
- [RISCV] Optimize xor/or with immediate in the zbs extension · bf773170
  Ben Shi authored May 25, 2021
  bf773170
May 24, 2021
- [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming... · b510e4cf
  Craig Topper authored May 24, 2021
  b510e4cf
- Revert "[NFC] remove explicit default value for strboolattr attribute in tests" · 4ab3041a
  serge-sans-paille authored May 24, 2021
  4ab3041a
- [NFC] remove explicit default value for strboolattr attribute in tests · bda6e5be
  serge-sans-paille authored May 23, 2021
  bda6e5be
- [RISCV] Optimize getVLENFactoredAmount function. · d70e9195
  luxufan authored May 24, 2021
  d70e9195
- [RISCV] Prevent store combining from infinitely looping · 7a211ed1
  Fraser Cormack authored May 21, 2021
  7a211ed1
May 20, 2021
- [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach... · e10958c8
  Jessica Clarke authored May 20, 2021
  e10958c8
- [RISCV] Ensure small mask BUILD_VECTORs aren't expanded · c74ab891
  Fraser Cormack authored May 19, 2021
  c74ab891
- [RISCV] Ensure shuffle splat operands are type-legal · 26bd2250
  Fraser Cormack authored May 18, 2021
  26bd2250
May 19, 2021
- [RISCV] Support INSERT_VECTOR_ELT into i1 vectors · ca2c245b
  Fraser Cormack authored May 18, 2021
  ca2c245b
May 18, 2021
- [RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns · 175bdf12
  Fraser Cormack authored May 17, 2021
  175bdf12
- [RISCV][test] Add new tests of or/xor in the zbs extension · 3cf7983c
  Ben Shi authored May 18, 2021
  3cf7983c
May 17, 2021
- [DAGCombiner] Relax an assertion to an early return · 85e31edd
  Fraser Cormack authored May 13, 2021
  85e31edd
- [RISCV] Optimize or/xor with immediate in the zbs extension · 7746e818
  Ben Shi authored May 17, 2021
  7746e818
- [RISCV][test] Add new tests of or/xor in the zbs extension · 1dfd7d50
  Ben Shi authored May 17, 2021
  1dfd7d50
May 14, 2021
- [RISCV] Add the DebugLoc parameter to getVLENFactoredAmount(). · b41e1306
  Hsiangkai Wang authored May 13, 2021
  b41e1306
May 13, 2021
- [RISCV][NFC] Simplify test run lines · 797e580d
  Fraser Cormack authored May 13, 2021
  797e580d
May 12, 2021
- [TargetLowering] Improve legalization of scalable vector types · c5ec00e6
  Fraser Cormack authored May 07, 2021
  c5ec00e6
- Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach... · 8d37411e
  Stefan Pintilie authored May 12, 2021
  8d37411e
May 11, 2021
- [RISCV] Regenerate stepvector.ll. NFC · d092dd56
  Craig Topper authored May 11, 2021
  d092dd56
- [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local · ec27c5f1
  Fangrui Song authored May 11, 2021
  ec27c5f1
- [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min. · ce6e4f27
  Craig Topper authored May 11, 2021
  ce6e4f27
- [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl. · dc00cbb5
  Craig Topper authored May 10, 2021
  dc00cbb5
- [RISCV] Fix the calculation of the offset of Zvlsseg spilling. · d8ec2b18
  Hsiangkai Wang authored May 10, 2021
  d8ec2b18
May 10, 2021
- [RISCV] Correct VL for fixed length masked scatter. · 80b95108
  Craig Topper authored May 10, 2021
  80b95108
- [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion · 6db0cedd
  Fraser Cormack authored May 07, 2021
  6db0cedd
May 06, 2021
- [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach... · 6c80361b
  Jessica Clarke authored May 06, 2021
  6c80361b
May 05, 2021
- Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach... · 897d7bce
  Jessica Clarke authored May 05, 2021
  897d7bce
- [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach... · 6e876f9d
  Jessica Clarke authored May 05, 2021
  6e876f9d
- [RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM · 61a46375
  Fraser Cormack authored May 05, 2021
  61a46375
- [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV · 437468f3
  Fraser Cormack authored May 05, 2021
  437468f3
- [RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR · 491a3d13
  Fraser Cormack authored May 05, 2021
  491a3d13
- [RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR · 3fbcf07a
  Fraser Cormack authored May 05, 2021
  3fbcf07a
- [RISCV][VP] Lower VP ISD nodes to RVV instructions · 6f17613b
  Fraser Cormack authored Apr 29, 2021
  6f17613b
- [RISCV] Cap legal fixed-length vectors to 256-element types · cd6a52fe
  Fraser Cormack authored May 04, 2021
  cd6a52fe
May 04, 2021
- [ValueTypes] Add MVTs for v256i16 and v256f16 · 6523ff6d
  Fraser Cormack authored May 04, 2021
  6523ff6d