Commits · d63d662d3cc51219fb08908ebea8d5851e53adb8 · Roger Ferrer / llvm-epi · GitLab

May 26, 2021
- [RISCV] Remove --riscv-no-aliases from RVV tests · d63d662d
  Jessica Clarke authored May 26, 2021
  d63d662d
- [RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI pass. · b2c7ac87
  Craig Topper authored May 26, 2021
  b2c7ac87
- [RISCV] Enable cross basic block aware vsetvli insertion · 1b47a3de
  Craig Topper authored May 25, 2021
  1b47a3de
- [SystemZ] Support i128 inline asm operands. · d058262b
  Jonas Paulsson authored Apr 19, 2021
  d058262b
- [AMDGPU] Fix function pointer argument bug in AMDGPU Propagate Attributes pass. · fcd32d62
  jweightma authored May 26, 2021
  fcd32d62
- [X86][AMX] Fix a bug on tile config. · 4ed2b6cc
  Luo, Yuanke authored May 26, 2021
  4ed2b6cc
- [ARM] Extra test for reverted WLS memset. NFC · a409fcdd
  David Green authored May 26, 2021
  
  a409fcdd
- [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads · 629e2b34
  Simon Pilgrim authored May 26, 2021
  
  629e2b34
- [AArch64] Generate LD1 for anyext i8 or i16 vector load · 8ac66d61
  Andrew Savonichev authored May 05, 2021
  8ac66d61
- [MC] Move elf-unique-sections-by-flags.ll to X86/ · ab8c4411
  Tomas Matheson authored May 26, 2021
  
  ab8c4411
- [MC][ELF] Emit unique sections for different flags · 165321b3
  Tomas Matheson authored May 12, 2021
  165321b3
- [AMDGPU][GlobalISel] Stop foldInsertEltToCmpSelect from changing reg banks · 96018499
  Mirko Brkusanin authored May 26, 2021
  96018499
- Revert "[AMDGPU][GlobalISel] Stop foldInsertEltToCmpSelect from changing reg banks" · 7386ad4e
  Mirko Brkusanin authored May 26, 2021
  7386ad4e
- [RISCV] Pre-commit fixed-length mask vselect tests · 7e27e427
  Fraser Cormack authored May 26, 2021
  7e27e427
- AArch64: support post-indexed stores to bfloat types. · 8c5ac18d
  Tim Northover authored May 26, 2021
  
  8c5ac18d
- [ARM] Add patterns for vmulh · 2cf0e52b
  David Green authored May 26, 2021
  2cf0e52b
May 25, 2021
- [ARM] Extra predicated tests for VMULH. NFC · 8cc437a8
  David Green authored May 25, 2021
  
  8cc437a8
- [SelectionDAG] Propagate scoped AA metadata when lowering mem intrinsics. · c9dd2992
  Michael Liao authored May 06, 2021
  c9dd2992
- Add pre-commit tests for [D102215](https://reviews.llvm.org/D102215 ). · 4df3b601
  Michael Liao authored May 25, 2021
  
  4df3b601
- [AMDGPU] Lower kernel LDS into a sorted structure · 8de4db69
  Stanislav Mekhanoshin authored May 19, 2021
  8de4db69
- [Hexagon] Improve argument packing in vector shuffle selection · e7c839b1
  Krzysztof Parzyszek authored May 04, 2021
  
  e7c839b1
- [AMDGPU][GlobalISel] Stop foldInsertEltToCmpSelect from changing reg banks · 18c54447
  Mirko Brkusanin authored May 25, 2021
  18c54447
- [AIX][AsmPrinter] Print Symbol in comments for TOC load · 882e4cbd
  Jinsong Ji authored May 25, 2021
  882e4cbd
- [SystemZ] Return true from preferZeroCompareBranch(). · e77cb4ae
  Jonas Paulsson authored May 25, 2021
  e77cb4ae
- BPF: Add more relocation kinds · 6a2ea846
  Yonghong Song authored May 18, 2021
  6a2ea846
- [X86][SSE] Regenerate vector shift codegen tests. NFCI. · e02a4f6b
  Simon Pilgrim authored May 25, 2021
  
  e02a4f6b
- [AArch64][SVE] Add fixed length codegen for FP_TO_{S,U}INT/{S,U}INT_TO_FP · f3c577ed
  Bradley Smith authored May 18, 2021
  f3c577ed
- [AArch64] Add tests for lowering of vector load + single extract. · 536447eb
  Florian Hahn authored May 25, 2021
  536447eb
- [ARM][NEON] Combine base address updates for vld1x intrinsics · 44843e2a
  Kristina Bessonova authored May 25, 2021
  44843e2a
- [llvm][ARM] Remove non-existent arm1176j-s CPU · 0cd2629d
  David Spickett authored May 24, 2021
  0cd2629d
- [RISCV] Optimize xor/or with immediate in the zbs extension · bf773170
  Ben Shi authored May 25, 2021
  bf773170
- AMDGPU/GlobalISel: Legalize G_[SU]DIVREM instructions · 90d78405
  Christudasan Devadasan authored Apr 12, 2021
  90d78405
May 24, 2021
- fix up test from D102742 · 7cd07d33
  Nick Desaulniers authored May 24, 2021
  7cd07d33
- [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming... · b510e4cf
  Craig Topper authored May 24, 2021
  b510e4cf
- [WebAssembly] Add NullifyDebugValueLists pass · a64ebb86
  Heejin Ahn authored May 23, 2021
  a64ebb86
- Revert "[NFC] remove explicit default value for strboolattr attribute in tests" · 4ab3041a
  serge-sans-paille authored May 24, 2021
  4ab3041a
- [NFC] remove explicit default value for strboolattr attribute in tests · bda6e5be
  serge-sans-paille authored May 23, 2021
  bda6e5be
- [X86] Call insertDAGNode on trunc/zext created in tryShiftAmountMod. · 3c0735c6
  Craig Topper authored May 24, 2021
  3c0735c6
- [Remarks] Add analysis remarks for memset/memcpy/memmove lengths · 095e91c9
  Jon Roelofs authored May 24, 2021
  095e91c9
- [RISCV] Optimize getVLENFactoredAmount function. · d70e9195
  luxufan authored May 24, 2021
  d70e9195