Commits · d6a0585dd1b8cc82e827e3218fe3b077d33c3ed1 · Roger Ferrer / llvm-epi · GitLab

Oct 27, 2022
- [SampleFDO] Compute and report profile staleness metrics · d6a0585d
  wlei authored Oct 24, 2022
  d6a0585d
- [AArch64] Adjust operand sequence for Add+Sub to combine more inline shift · ada9ab61
  chenglin.bi authored Oct 27, 2022
  ada9ab61
- [CodeGen] Improve large stack frame diagnostic · 2e1e2f52
  Paul Kirth authored Oct 21, 2022
  2e1e2f52
- [NFC][PhaseOrdering] Add new test for SROA misplacement · 70324cd8
  Roman Lebedev authored Oct 27, 2022
  
  70324cd8
- [dwarfdump] Fix bogus incompatible tag warning · d7755654
  Jonas Devlieghere authored Oct 26, 2022
  d7755654
Oct 26, 2022
- [RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven. · e94dc58d
  Craig Topper authored Oct 26, 2022
  e94dc58d
- [InstCombine] add tests for demanded bits of sub; NFC · 7d3a37a4
  Sanjay Patel authored Oct 26, 2022
  
  7d3a37a4
- [RISCV] Add tests for fixed vector sshl_sat/ushl_sat. NFC · 0a03240f
  Craig Topper authored Oct 26, 2022
  
  0a03240f
- [MIPS] Fix useDeprecatedPositionallyEncodedOperands errors. · 26fdad03
  James Y Knight authored Sep 19, 2022
  26fdad03
- [InstCombine] add tests for demanded bits of sub; NFC · 1bd856fb
  Sanjay Patel authored Oct 26, 2022
  
  1bd856fb
- [SDAG] avoid vector extract/insert around binop · 54eeadcf
  Sanjay Patel authored Oct 26, 2022
  54eeadcf
- [OpenMP][FIX] Do not add custom state machine eagerly in LTO runs · 41a278f5
  Johannes Rudolf Doerfert authored Oct 25, 2022
  41a278f5
- Reland "[PGO] Make emitted symbols hidden" · 443e2a10
  Alex Brachet authored Oct 26, 2022
  443e2a10
- [RISCV] add svinval extension · 7d7940fd
  Piyou Chen authored Oct 26, 2022
  7d7940fd
- [RISCV] Use vslide1down for i64 insertelt on RV32. · a61b7488
  Craig Topper authored Oct 26, 2022
  a61b7488
- [AMDGPU][test] precommiting tests for D136663 · 14fb4040
  Yashwant Singh authored Oct 26, 2022
  14fb4040
- [FuncSpec] Add a testcase for the treatment of constant and unused arguments · 5ea8951b
  Momchil Velikov authored Oct 26, 2022
  5ea8951b
- [TableGen] Add log bang operator · 64d5aedd
  Michael Maitland authored Sep 16, 2022
  64d5aedd
- [x86] add tests for extract + insert of vector shift amount; NFC · ef9dfcd6
  Sanjay Patel authored Oct 25, 2022
  
  ef9dfcd6
- [UpdateTestChecks] Sync flags in update_mir_test_checks.py with MIFlags · 7bc7f2da
  Anton Sidorenko authored Oct 18, 2022
  7bc7f2da
- Revert "[FuncSpec] Fix specialisation based on literals" · 99015839
  Momchil Velikov authored Oct 26, 2022
  99015839
- [UpdateTestChecks] Precommit test for D136170 · 16fb9150
  Anton Sidorenko authored Oct 20, 2022
  
  16fb9150
- [FuncSpec] Compute specialisation gain even when forcing specialisation · 606d25e5
  Momchil Velikov authored Oct 26, 2022
  606d25e5
- [FuncSpec] Fix specialisation based on literals · a8b0f580
  Momchil Velikov authored Oct 25, 2022
  a8b0f580
- [SelectionDAG] Clamp stack alignment for memset, memmove · 21f23a37
  Haohai Wen authored Oct 26, 2022
  21f23a37
- [GlobalISel] Add Predicates to GICombineRule · 63390dcc
  Pierre van Houtryve authored Oct 25, 2022
  63390dcc
- [AMDGPU] Autogenerate llvm.amdgcn.fcmp.ll · c1b2920c
  Pierre van Houtryve authored Oct 24, 2022
  c1b2920c
- [GlobalISel][AArch64] Fix miscompile caused by wrong G_ZEXT selection in GISel · 9403a8bc
  chenglin.bi authored Oct 26, 2022
  9403a8bc
- [X86] Enable reassociation for ADD instructions · d24c93cc
  Guozhi Wei authored Oct 26, 2022
  d24c93cc
- SimplifyLibCalls: Add missing testcase for sincospi · 8acddef9
  Matt Arsenault authored Oct 25, 2022
  8acddef9
- Revert "Update supported features in the generic CPU configuration" · fc40c739
  Douglas Yung authored Oct 25, 2022
  fc40c739
- [FuncSpec] Fix missed opportunities for function specialisation · 1a525dec
  Momchil Velikov authored Oct 25, 2022
  1a525dec
Oct 25, 2022
- [LV][RISCV] Disable vectorization of epilogue loops · 269bc684
  Philip Reames authored Oct 25, 2022
  269bc684
- [LoopPeeling] Add flag to disable support for peeling loops with non-latch exits · d1b19da8
  Alina Sbirlea authored Oct 24, 2022
  d1b19da8
- [FuncSpec] Consider small noinline functions for specialisation · c47739b4
  Momchil Velikov authored Oct 25, 2022
  c47739b4
- Update supported features in the generic CPU configuration · 11afbf39
  Dan Gohman authored Oct 18, 2022
  11afbf39
- [CUDA, NVPTX] Added basic __bf16 support for NVPTX. · 0e8a414a
  Artem Belevich authored Oct 19, 2022
  0e8a414a
- [AArch64]SME2 single-multi and multi-multi INT dot product instructions[part2] · 9fbd57fb
  Caroline Concatto authored Oct 22, 2022
  9fbd57fb
- [AArch64]SME2 single-multi and multi-multi INT/FP dot product instructions · 070f4146
  Caroline Concatto authored Oct 22, 2022
  070f4146
- [AMDGPU] Fix delay alu for VOPD with src2acc · 01b8140d
  Joe Nash authored Oct 20, 2022
  01b8140d