Commits · d72545b293f9fe33fb6c7f5ab611f48860fd8d16 · Roger Ferrer / llvm-epi · GitLab

Jun 02, 2023
- [SVE ACLE] Extend IR combines for fmul, fsub, fadd to cover _u variants · dc63b35b
  Jolanta Jensen authored May 17, 2023
  dc63b35b
- [AArch64] Don't use tbl lowering if ZExt can be folded into user. · e97b8a7e
  Florian Hahn authored Jun 02, 2023
  e97b8a7e
Jun 01, 2023
- [SDAG] Preserve unpredictable metadata, teach X86CmovConversion to respect this metadata · 09515f2c
  Dávid Bolvanský authored Jun 01, 2023
  09515f2c
- [AArch64] Increase the cost of i1 inserts / extracts · eb764a7f
  David Green authored Jun 01, 2023
  eb764a7f
- [AArch64] Adjust costs of i1 and/or/xor reductions · e79fac29
  David Green authored Jun 01, 2023
  e79fac29
May 30, 2023
- [CodeGen] Refactor IR generation functions to use IRBuilder in ComplexDeinterleaving pass · 40a81d31
  Igor Kirillov authored Apr 19, 2023
  40a81d31
May 29, 2023
- [AArch64] Remove unused declaration tryParseMRSSystemRegister · d0354892
  Kazu Hirata authored May 29, 2023
  d0354892
- [AArch64] Remove unused declaration legalizeShuffleVector · c65fd1ce
  Kazu Hirata authored May 29, 2023
  c65fd1ce
- [AArch64] Remove unused declaration LowerSCALAR_TO_VECTOR · 72c17a0d
  Kazu Hirata authored May 29, 2023
  72c17a0d
May 26, 2023
- [AArch64] merge scaled and unscaled zero narrow stores. · 0c93879d
  Zain Jaffal authored May 19, 2023
  0c93879d
May 24, 2023
- LLVM_FALLTHROUGH => [[fallthrough]]. NFC · 6006d43e
  Craig Topper authored May 24, 2023
  6006d43e
May 23, 2023
- [AArch64][LV] Disable maximising bandwidth for streaming compatible sve · 7489301c
  Dinar Temirbulatov authored May 23, 2023
  7489301c
- [AArch64] Avoid RegScavenger::forward in AArch64SpeculationHardening · 910af0e7
  Jay Foad authored May 15, 2023
  910af0e7
May 22, 2023
- [SME2/SVE2p1] Extend llvm.aarch64.sve.convert.to/from.svbool to accept target("aarch64.svcount") · 11926e61
  Sander de Smalen authored May 22, 2023
  11926e61
- [SME2/SVE2p1] Change psel intrinsic such that the result/first operand are not overloaded. · 437a516d
  Sander de Smalen authored May 22, 2023
  437a516d
- [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for ld1/ldnt1/st1/stnt1 · 387c49f6
  Sander de Smalen authored May 22, 2023
  387c49f6
- [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for sel · d33910a8
  Sander de Smalen authored May 22, 2023
  d33910a8
May 19, 2023
- [AArch64][GlobalISel] Selection support for v8s8, v4s16, v16s8 G_INSERT_VECTOR_ELT with GPR scalar · e291179e
  Vladislav Dzhidzhoev authored Mar 22, 2023
  e291179e
- Revert "[RFC][MC][MachO]Only emits compact-unwind format for "canonical"... · 4980eead
  Nico Weber authored May 19, 2023
  4980eead
May 18, 2023
- [AArch64] Predicate for ROR immediate · 2f7be446
  Evandro Menezes authored May 17, 2023
  2f7be446
- [RFC][MC][MachO]Only emits compact-unwind format for "canonical" personality... · 09aaf53a
  Vy Nguyen authored Feb 28, 2023
  09aaf53a
- [AArch64][LoopVectorize] Enable tail-folding of simple loops on neoverse-v1 · c7dbe326
  David Sherwood authored Apr 25, 2023
  c7dbe326
May 17, 2023
- [CodeGen] Replace CCState's getNextStackOffset with getStackSize (NFC) · 01a79674
  Sergei Barannikov authored May 01, 2023
  01a79674
- [AArch64] Sink operands for faster bitselect vector instructions · 726785b1
  Pranav Kant authored May 10, 2023
  726785b1
- [AArch64][NFC] Refactor the tail-folding option · 7beb2ca8
  David Sherwood authored Apr 20, 2023
  7beb2ca8
May 16, 2023
- [SVE ACLE] Change the lowering of SVE integer builtins · 105d63a2
  Jolanta Jensen authored May 12, 2023
  105d63a2
- [AArch64] Combine add(extract v1i64) into v1i64 add · 198f6a9f
  David Green authored May 16, 2023
  198f6a9f
- [AArch64] Use correct IRBuilder in InstCombine hooks · 724f4a5b
  Nikita Popov authored May 16, 2023
  724f4a5b
- [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for pext (multi) · 9b5f1971
  Sander de Smalen authored May 16, 2023
  9b5f1971
- [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for pext (single) · 094005eb
  Sander de Smalen authored May 16, 2023
  094005eb
- [AArch64] Change the type of i64 neon shifts to v1i64 · 8178de32
  David Green authored May 16, 2023
  8178de32
- [KnownBits] Define and use intersectWith and unionWith · d8229e2f
  Jay Foad authored May 10, 2023
  d8229e2f
May 15, 2023
- [AArch64][CostModel] Add costs for fixed operations when using fixed vectors over SVE. · 73668cce
  Dinar Temirbulatov authored May 15, 2023
  73668cce
- [AArch64] Update FP16 vector cmp costs · 1ba9ec0d
  David Green authored May 14, 2023
  1ba9ec0d
May 14, 2023
- [MC] Remove redundant classof definitions for MCTargetDesc's derived classes · 7f2db4db
  Fangrui Song authored May 14, 2023
  
  7f2db4db
- [LegalizeVectorOps][AArch64][RISCV][X86] Use OpVT for ISD::SETCC in LegalizeVectorOps. · 9ad9380f
  Craig Topper authored May 13, 2023
  9ad9380f
May 13, 2023
- [llvm] Migrate {starts,ends}with_insensitive to {starts,ends}_with_insensitive (NFC) · 6c3ea866
  Kazu Hirata authored May 12, 2023
  6c3ea866
May 12, 2023
- [DAGCombiner][AArch64][VE] Teach BuildUDIV/SDIV to use 2x mul when mulh/mul_lohi are not available. · a983ef2c
  Craig Topper authored May 12, 2023
  a983ef2c
- [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for while* · c8926644
  Sander de Smalen authored May 12, 2023
  c8926644
- [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for ptrue/cntp · 3b95b818
  Sander de Smalen authored May 12, 2023
  3b95b818