Commits · d72545b293f9fe33fb6c7f5ab611f48860fd8d16 · Roger Ferrer / llvm-epi · GitLab

Jun 02, 2023
- [RISCV] Modify a tablegen multiclass for a future patch. NFC · 76cc78dc
  Craig Topper authored Jun 01, 2023
  76cc78dc
- [RISCV][GlobalISel] Remove unused variable 'Index' (NFC) · 0a043e6c
  Jie Fu authored Jun 02, 2023
  0a043e6c
- [RISCV][GlobalISel] Add lowerCall for calling convention · 9c6bee65
  Nitin John Raj authored Jun 01, 2023
  9c6bee65
- [RISCV] Separate slideup/down pseudoinstructions from FMA instructions earlier... · 37cfcfce
  Craig Topper authored Jun 01, 2023
  37cfcfce
- [RISCV] Move vslideup/down tablegen classes together. NFC · 94a8be41
  Craig Topper authored Jun 01, 2023
  
  94a8be41
Jun 01, 2023
- [RISCV] Rename VPseudoBinaryTailPolicy to VPseudoTernaryMaskPolicy. NFC · f166b397
  Craig Topper authored Jun 01, 2023
  
  f166b397
- [SDAG] Preserve unpredictable metadata, teach X86CmovConversion to respect this metadata · 09515f2c
  Dávid Bolvanský authored Jun 01, 2023
  09515f2c
- [RISCV][NFC] Add isF argument to SchedSEWSet · 78a22401
  Pengcheng Wang authored Jun 01, 2023
  78a22401
May 31, 2023
- [RISCV] Change LdPat and StPat from multiclass to class. NFC · cf229033
  Craig Topper authored May 31, 2023
  cf229033
- [RISCV] Use class and inheritance instead of multiclass for some vector isel patterns. NFC · 6cc17b28
  Craig Topper authored May 31, 2023
  
  6cc17b28
- [RISCV] Lower extern_weak symbols using the GOT for the medany model · a178ba9f
  Jessica Clarke authored May 31, 2023
  a178ba9f
- [RISCV] Add new lga pseudoinstruction · 9b55e5d4
  Jessica Clarke authored May 31, 2023
  9b55e5d4
- [RISCV][InsertVSETVLI] Relax tail policy more often for vmv.s.x · f3b39cea
  Luke Lau authored May 31, 2023
  f3b39cea
- [RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block · badf11de
  Luke Lau authored May 31, 2023
  badf11de
- [RISCV][InsertVSETVLI] Move vmv.s.x SEW check into getDemandedBits. NFC · 257cc049
  Luke Lau authored May 26, 2023
  257cc049
- Revert "[RISCV] Add Zvfhmin extension for clang." · a5e5eea2
  Craig Topper authored May 31, 2023
  a5e5eea2
- Revert "[RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block" · 319adf5d
  Luke Lau authored May 31, 2023
  319adf5d
- [RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block · 0ba41dd3
  Luke Lau authored May 31, 2023
  0ba41dd3
- [RISCV] Fix an unused variable warning · 6eef8d9b
  Kazu Hirata authored May 31, 2023
  6eef8d9b
- [RISCV] Use v(f)slide1down for shuffle+insert idiom · e6931813
  Philip Reames authored May 31, 2023
  e6931813
- [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT · 548fa1d3
  LiaoChunyu authored May 31, 2023
  548fa1d3
- [RISCV] Add Zvfhmin extension for clang. · 35a00792
  Jianjian GUAN authored May 25, 2023
  35a00792
- [RISCV] Merge emitDirectiveOptionArchPlus and emitDirectiveOptionArchMinus... · ac1df223
  Craig Topper authored May 30, 2023
  ac1df223
- [RISCV] Strengthen some SDTypeProfiles to reduce isel table size. · 0a4ba485
  Craig Topper authored May 30, 2023
  
  0a4ba485
- [RISCV] Fix selection for some unmasked vp SDNode. · 62307f6d
  Jianjian GUAN authored May 30, 2023
  62307f6d
- [RISCV] Allow FWMUL formation for an FP extend used twice by the same multiply. · 45416335
  Craig Topper authored May 30, 2023
  
  45416335
May 30, 2023
- [RISCV] Add RISCVISD::VFWMUL_VL. Use it to replace isel patterns with a DAG combine. · 463f50b4
  Craig Topper authored May 30, 2023
  463f50b4
- [RISCV][GlobalISel] Add lowerFormalArguments for calling convention · af8e3861
  Nitin John Raj authored May 30, 2023
  af8e3861
- [RISCV] Use v(f)slide1up for shuffle+insert idiom · 544a240f
  Philip Reames authored May 30, 2023
  544a240f
- [RISCV][NFC] Make Reduction scheduler resources SEW aware · d70573b1
  Michael Maitland authored May 25, 2023
  d70573b1
- [RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all <XLEN floats on soft ABIs · c4efcd69
  Alex Bradbury authored May 30, 2023
  c4efcd69
- [RISCV] Teach performCombineVMergeAndVOps to handle instructions FMA instructions. · 9239d3a3
  Craig Topper authored May 29, 2023
  9239d3a3
- [RISCV] Fix unmasked vp_abs select. · 071e9d7b
  Jianjian GUAN authored May 29, 2023
  071e9d7b
May 27, 2023
- [RISCV] Add isel patterns to form tail undisturbed vfwadd.wv from fpextend_vl+vfwadd_vl+vp_merge. · 28ab0322
  Craig Topper authored May 26, 2023
  28ab0322
May 26, 2023
- [RISCV] Simplify code in LowerIS_FPCLASS. NFC · 9b9e9aba
  Craig Topper authored May 26, 2023
  
  9b9e9aba
- [RISCV] Remove extra MVT::Other result from creation of RISCVISD::FCLASS_VL. · 1fea6bd8
  Craig Topper authored May 26, 2023
  
  1fea6bd8
- [RISCV] Tighten type constraint for RISCVISD::FCLASS_VL. · dcd5f312
  Craig Topper authored May 26, 2023
  
  dcd5f312
- [RISCV] Fix typo VLUpperBound to VLEN in SiFive7. NFC. · c73c7678
  Michael Maitland authored May 25, 2023
  c73c7678
- [RISCV] Support '.option arch' directive · 9e8ed340
  luxufan authored May 26, 2023
  9e8ed340
- [RISCV] Don't scalarize vector stores if volatile · 90c4db4a
  Luke Lau authored May 25, 2023
  90c4db4a