Commits · d77ae7f2513504655e555cd326208598093d66e2 · Roger Ferrer / llvm-epi · GitLab

Dec 07, 2022
- [amdgpu] Reimplement LDS lowering · d77ae7f2
  Jon Chesterfield authored Dec 07, 2022
  d77ae7f2
- Generate DXIL Shader hash · c861ea87
  Chris Bieneman authored Dec 05, 2022
  c861ea87
- [SPARC] Lower SELECT_CC to MOVr on 64-bit target whenever possible · f8f41c3f
  Koakuma authored Dec 07, 2022
  f8f41c3f
- Revert "[SPARC] Mark the %g0 register as constant & use it to materialize zeros" · 7806f86a
  Brad Smith authored Dec 07, 2022
  7806f86a
- AArch64: emit `fcmp ord %a, zeroinitializer` as a single fcmeq. · 6b98824a
  Tim Northover authored Nov 10, 2022
  6b98824a
- [SPARC] Mark the %g0 register as constant & use it to materialize zeros · 2c41310f
  Koakuma authored Dec 07, 2022
  2c41310f
- [AMDGPU] Enable OMod on more VOP3 instructions · bbfbec94
  Joe Nash authored Dec 02, 2022
  bbfbec94
- [GlobalISel] Add a new G_INVOKE_REGION_START instruction to fix an EH bug. · 53445f5b
  Amara Emerson authored Nov 13, 2022
  53445f5b
- [RISCV] Remove pseudos for whole register load, store, and move. · f1fd5c9b
  Craig Topper authored Dec 07, 2022
  f1fd5c9b
- [RISCV] Replace uses of hasStdExtC with COrZca. · 938d0d6d
  Craig Topper authored Dec 07, 2022
  938d0d6d
- [AMDGPU][GlobalISel] Fix legalizing image intrinsics for new types · fe42ebe4
  Mirko Brkusanin authored Dec 07, 2022
  fe42ebe4
- [AMDGPU] Add gfx11 runline to omod test. NFC · c6c4f54e
  Joe Nash authored Dec 07, 2022
  
  c6c4f54e
- [X86] Pre-commit test for pr59305 · fc16ca71
  Phoebe Wang authored Dec 08, 2022
  
  fc16ca71
- Automate tests. · f7d426b3
  Doru Bercea authored Dec 06, 2022
  
  f7d426b3
- [X86] combine-and.ll - add some 256/512-bit test coverage for D138521 · 519adee2
  Simon Pilgrim authored Dec 07, 2022
  
  519adee2
- [X86] combine-and.ll - add AVX1 test coverage · abe6dbee
  Simon Pilgrim authored Dec 07, 2022
  
  abe6dbee
- [llvm] Auto-cleanup left-over file from earlier version of this test on bots · bfe292b0
  Nico Weber authored Dec 07, 2022
  bfe292b0
- Fix a typo ll->llc in test · 3abdd9b9
  Haojian Wu authored Dec 07, 2022
  
  3abdd9b9
- Add implementation isTargetCanonicalConstantNode for hexagon. · a2215149
  Haojian Wu authored Dec 07, 2022
  a2215149
- [AMDGPU] G_IS_FPCLASS lower() support for IEEE fp types · 587747d8
  Janek van Oirschot authored Dec 06, 2022
  587747d8
- [MachineCombiner] Extend reassociation logic to handle inverse instructions · f8ed7093
  Anton Sidorenko authored Oct 14, 2022
  f8ed7093
- [AMDGPU] Fix wide spills · 1e3abd82
  Piotr Sobczak authored Dec 02, 2022
  1e3abd82
- [SVE] Change some bfloat lane intrinsics to use i32 immediates · bfb6f47e
  David Sherwood authored Nov 28, 2022
  bfb6f47e
- [PowerPC] Support test data class intrinsic of 128-bit float · 62f20f51
  Qiu Chaofan authored Dec 07, 2022
  62f20f51
- [VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support." · 0f8c761c
  Yeting Kuo authored Dec 07, 2022
  0f8c761c
- [AMDGPU] Handle `min(max(x, y), max(min(x, y), z))` in med3 combines · bcfdaa96
  Justin Bogner authored Dec 06, 2022
  bcfdaa96
- [AMDGPU] Handle nnan and fast on the call in fpmed3 patterns · 916ae0a0
  Justin Bogner authored Dec 06, 2022
  916ae0a0
- [AMDGPU] Precommit GISel test for min(max(x, y), max(min(x, y), z)) -> med3 · f1353d2f
  Justin Bogner authored Dec 06, 2022
  f1353d2f
- [Propeller] Use Fixed MBB ID instead of volatile MachineBasicBlock::Number. · 6015a045
  Rahman Lavaee authored Dec 06, 2022
  6015a045
- Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support." · 7883e5b0
  Kazu Hirata authored Dec 06, 2022
  7883e5b0
- [AMDGPU] Precommit GISel test showing missing med3 combines · 6ec24c1d
  Justin Bogner authored Dec 06, 2022
  6ec24c1d
- [RISCV] Codegen support for Zfhmin. · 7b50c183
  Monk Chiang authored Nov 30, 2022
  7b50c183
- [VP][RISCV] Add vp.fshl/fshr and RISC-V support. · 70de0e01
  Yeting Kuo authored Nov 20, 2022
  70de0e01
- [RISCV] Move VSPILL/VRELOAD expansion for vector tuples to eliminateFrameIndex. · 8d30b9e6
  Craig Topper authored Dec 06, 2022
  8d30b9e6
- [Mips] Convert a test to check 'target=...' · a4595298
  Paul Robinson authored Dec 06, 2022
  a4595298
Dec 06, 2022
- [RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility. · 1806ce90
  Craig Topper authored Dec 06, 2022
  1806ce90
- Reapply "[mlgo] Dependency-free training mode logger" · 4c97745b
  Mircea Trofin authored Dec 06, 2022
  4c97745b
- [ARM] IselLowering unsigned overflow to crash using APInt in PerformSHLSimplify · ee31a4a7
  Peter Rong authored Dec 02, 2022
  ee31a4a7
- Revert "[mlgo] Dependency-free training mode logger" · 8abe7b11
  Florian Hahn authored Dec 06, 2022
  8abe7b11
- Revert "[amdgpu] Reimplement LDS lowering" · a862d09a
  Nico Weber authored Dec 06, 2022
  a862d09a