Commits · d896f22fdaadb9abb6654a52a79e7e45c8af66ec · Roger Ferrer / llvm-epi · GitLab

Sep 04, 2021
- [X86][SLM] WriteVecIMul instructions only take 1uop (REAPPLIED) · 2005ae15
  Simon Pilgrim authored Sep 04, 2021
  2005ae15
- [WebAssembly] Support opaque pointers in AddMissingPrototypes · 66a54af9
  Nikita Popov authored Sep 03, 2021
  66a54af9
- Revert "[AArch64] Implement target hook function to decide folding (mul (add x, c1), c2)" · c7f50a44
  Kevin Athey authored Sep 03, 2021
  c7f50a44
- [AArch64] Implement target hook function to decide folding (mul (add x, c1), c2) · 095bea23
  Ben Shi authored Aug 27, 2021
  095bea23
Sep 03, 2021
- [ARM] Add patterns for store(fptosisat(..)) · adfd12e6
  David Green authored Sep 03, 2021
  adfd12e6
- [ARM] Add VFP lowering for fptosi.sat · f37e1322
  David Green authored Sep 03, 2021
  f37e1322
- Add missing `REQUIRES: asserts` to combine-icmp-to-lhs-known-bits.mir · bd22a99c
  Jessica Paquette authored Sep 03, 2021
  
  bd22a99c
- [RISCV] Change how we encode AVL operands in vector pseudoinstructions to use GPRNoX0. · 75620fad
  Craig Topper authored Sep 03, 2021
  75620fad
- [AArch64][GlobalISel] Support for folding G_ROTR as shifted operands. · 6d9505b8
  Amara Emerson authored Sep 02, 2021
  6d9505b8
- [PowerPC] Enable fast-isel on AIX 64 subtarget · d0f9553e
  Qiu Chaofan authored Sep 03, 2021
  d0f9553e
- Revert "[HardwareLoops] Change order of SCEV expression construction for InitLoopCount." · 34badc40
  Chen Zheng authored Sep 03, 2021
  34badc40
- [AMDGPU] Process any power of 2 in optimizeCompareInstr · 78fbd1aa
  Stanislav Mekhanoshin authored Sep 02, 2021
  78fbd1aa
- [AMDGPU] Fold immediates in the optimizeCompareInstr · 2cfda6a6
  Stanislav Mekhanoshin authored Sep 02, 2021
  2cfda6a6
- [GlobalISel] Combine icmp eq/ne x, 0/1 -> x when x == 0 or 1 · 844d8e03
  Jessica Paquette authored Sep 01, 2021
  844d8e03
Sep 02, 2021
- [asan] Fixed link error by setting jump symbol to R_X86_64_PLT32. · cf53c6c9
  Kirill Stoimenov authored Sep 02, 2021
  cf53c6c9
- [WebAssembly] Add Wasm SjLj support · 28780e59
  Heejin Ahn authored Aug 01, 2021
  28780e59
- [MipsISelLowering] avoid emitting libcalls to __multi3 · 6860b136
  Nick Desaulniers authored Sep 02, 2021
  6860b136
- [X86] Remove isel predicates for xgetbv/xsetbv instructions so they can work on Windows. · 3e89cc5c
  Craig Topper authored Sep 02, 2021
  3e89cc5c
- [RISCV] Improve shrink wrap test (NFC) · cd6064bb
  Evandro Menezes authored Sep 02, 2021
  cd6064bb
- [AMDGPU] Use S_BITCMP0_* to replace AND in optimizeCompareInstr · 832c87b4
  Stanislav Mekhanoshin authored Sep 01, 2021
  832c87b4
- [X86][SSE] combineMulToPMADDWD - improve recognition of sign/zero extended upper bits · d66d520f
  Simon Pilgrim authored Sep 02, 2021
  d66d520f
- [RISCV] Add Zba command line to rv64i-exhaustive-w-insts.ll · 498e8ae4
  Craig Topper authored Sep 02, 2021
  498e8ae4
- [RISCV] Remove stale TODOs from test. NFC · eaa56058
  Craig Topper authored Sep 02, 2021
  eaa56058
- [AArch64][SVE] Workaround incorrect types when lowering fixed length gather/scatter · 14e1a4a6
  Bradley Smith authored Sep 02, 2021
  14e1a4a6
- [RISCV] Teach instruction selection to elide sext.w in some cases. · b5fd6b46
  Craig Topper authored Sep 02, 2021
  b5fd6b46
- [RISCV] Enable shrink wrap by default · 5ebdb07e
  Evandro Menezes authored Aug 09, 2021
  5ebdb07e
- [RISCV] Split PseudoVSETVLI into 2 instructions to allow different register classes for rs1. · e4e69ba4
  Craig Topper authored Sep 01, 2021
  e4e69ba4
- [AMDGPU] Add merging into S_BUFFER_LOAD_DWORDX8_IMM · 30d6c39b
  Piotr Sobczak authored Aug 30, 2021
  30d6c39b
- [ARM] Add a tail-predication loop predicate register · 9cb8f4d1
  David Green authored Sep 02, 2021
  9cb8f4d1
- Revert @llvm.isnan intrinsic patchset. · 3f1f08f0
  Roman Lebedev authored Sep 02, 2021
  3f1f08f0
- [X86] Fold PMADD(x,0) or PMADD(0,x) -> 0 · b0acd6c3
  Simon Pilgrim authored Sep 02, 2021
  b0acd6c3
- [X86][SSE] Add combine-pmadd.ll for PMADDWD/VPMADDUBSW combines · a84c0841
  Simon Pilgrim authored Sep 01, 2021
  a84c0841
- [RISCV][test] Add more tests for (mul (add x, c1), c2) · 9621bbdf
  Ben Shi authored Aug 23, 2021
  9621bbdf
- [RISCV][test] Add tests for optimization with SH*ADD in the zba extension · e47ab563
  Ben Shi authored Aug 30, 2021
  e47ab563
- [LegalizeTypes][VP] Add splitting support for binary VP ops · ef78f210
  Fraser Cormack authored Aug 11, 2021
  ef78f210
- [DAGCombine] Add node level checks for fp-contract and fp-ninf in... · 0baace53
  Abinav Puthan Purayil authored Aug 02, 2021
  0baace53
- [AArch64][test] Add new tests for (mul (add x, c0), c1) · 14500628
  Ben Shi authored Aug 27, 2021
  14500628
- Revert "[AArch64][GlobalISel] Legalize bswap <2 x i16>" · 9237eda3
  Jon Roelofs authored Sep 01, 2021
  9237eda3
- [AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstr · f3645c79
  Stanislav Mekhanoshin authored Sep 01, 2021
  f3645c79
- [AMDGPU] Introduce optimizeCompareInstr · bf77b112
  Stanislav Mekhanoshin authored Aug 31, 2021
  bf77b112