Commits · d8c817a9cdf478b21462101e603b0ad0e91f024a · Roger Ferrer / llvm-epi · GitLab

Jul 15, 2022
- [RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel. · 79016f6e
  Craig Topper authored Jul 14, 2022
  79016f6e
- [RISCV] Fix mistake in RISCVTTIImpl::getIntImmCostInst. · bc0d6565
  Craig Topper authored Jul 14, 2022
  bc0d6565
- [AMDGPU] Update the mechanism used to check for cycles and add eges in power-sched mutation · 8a12f20e
  jeff authored Jul 13, 2022
  
  8a12f20e
- [llvm-dwp] Add SHF_COMPRESSED support and remove .zdebug support · 141c9d77
  Fangrui Song authored Jul 14, 2022
  141c9d77
- [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. · dcfc1fd2
  Craig Topper authored Jul 14, 2022
  dcfc1fd2
- [RISCV] Make TuneSiFive7 depend on TuneNoDefaultUnroll instead of listing it for every SiFive7 CPU · 9913ea49
  Craig Topper authored Jul 14, 2022
  
  9913ea49
- Remove zlibgnu support in llvm-mc · d63ec445
  David Blaikie authored Jul 14, 2022
  d63ec445
Jul 14, 2022
- [AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable. · 2e29b013
  Alexander Timofeev authored Jun 21, 2022
  2e29b013
- [clang][CodeGen] add fn_ret_thunk_extern to synthetic fns · 140bfdca
  Nick Desaulniers authored Jul 14, 2022
  140bfdca
- [GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT. · d4f84df0
  Amara Emerson authored Jul 14, 2022
  d4f84df0
- [RISCV] Add a RISCV specific CodeGenPrepare pass. · 1a8468ba
  Craig Topper authored Jul 14, 2022
  1a8468ba
- [MachineCombiner] Don't compute the latency of transient instructions · 2f11b3a6
  Guozhi Wei authored Jul 14, 2022
  2f11b3a6
- [SimplifyIndVar] Use enum class for ExtendKind. NFC · 0e718443
  Craig Topper authored Jul 14, 2022
  0e718443
- [SCEV] Avoid creating unnecessary SCEVs for SelectInsts. · e7ec1746
  Florian Hahn authored Jul 14, 2022
  e7ec1746
- [RISCV] Disable subregister liveness by default · d1a5669f
  Fraser Cormack authored Jul 13, 2022
  d1a5669f
- [SCEVExpander] Allow udiv with isKnownNonZero(RHS) + add vscale case · 3bc09c7d
  Philip Reames authored Jul 14, 2022
  3bc09c7d
- Revert "[UnifyLoopExits] Reduce number of guard blocks" · 58fec782
  Brendon Cahoon authored Jul 14, 2022
  58fec782
- [NFC][Metadata] Change MDNode::operands()'s return type from op_range to ArrayRef<MDOperand> · d71128d9
  Dawid Jurczak authored Jul 14, 2022
  d71128d9
- [Reassociate] Cleanup minor missed optimizations · 230c8c56
  Warren Ristow authored Jul 14, 2022
  230c8c56
- [Bitcode] Report metadata decoding error more gracefully · 159feac1
  Nikita Popov authored Jul 14, 2022
  
  159feac1
- Revert "[StructurizeCFG] Improve basic block ordering" · c945d88d
  Brendon Cahoon authored Jul 14, 2022
  c945d88d
- Turn on flag to not re-run simplification pipeline. · 846d10f1
  Alina Sbirlea authored Jun 13, 2022
  846d10f1
- [LoopPredication] Use isSafeToExpandAt() member function (NFC) · 9e6e631b
  Nikita Popov authored Jul 14, 2022
  9e6e631b
- [SCEVExpander] Make CanonicalMode handing in isSafeToExpand() more robust (PR50506) · dcf4b733
  Nikita Popov authored Jul 13, 2022
  dcf4b733
- [IndVars] Eliminate redundant type cast between unsigned integer and float · fc6092fd
  zhongyunde authored Jul 14, 2022
  fc6092fd
- [JITLink] Silence unused variable warning. (NFC) · 18a6ab5b
  Sunho Kim authored Jul 14, 2022
  
  18a6ab5b
- Revert "[ORC] Add a shared-memory based orc::MemoryMapper." · 3e9cc543
  Cullen Rhodes authored Jul 14, 2022
  3e9cc543
- Revert "[ORC] Fix compilation on mingw" · f3eacb4f
  Cullen Rhodes authored Jul 14, 2022
  f3eacb4f
- [AMDGPU] Update LiveVariables after killing an immediate def · e45aa230
  Jay Foad authored Jul 13, 2022
  e45aa230
- [IndVars] Make sure header phi simplification preserves LCSSA form · 7a43b382
  Nikita Popov authored Jul 14, 2022
  7a43b382
- [AArch64][NFC] Drop 'V' from ASIMD FP convert, other, D/Q-form regex · 055b409c
  Cullen Rhodes authored Jul 13, 2022
  055b409c
- [LoongArch] Implement OR combination to generate bstrins.w/d · 9b87ad33
  Weining Lu authored Jul 13, 2022
  9b87ad33
- [ORC] Fix compilation on mingw · 46b1a7c5
  Martin Storsjö authored Jul 14, 2022
  46b1a7c5
- [SCCP] Make check for unknown/undef in unary op handling more explicit (NFCI) · ebc54e0c
  Nikita Popov authored Jul 14, 2022
  ebc54e0c
- [CodeGen] Move instruction predicate verification to emitInstruction · 3e0bf1c7
  David Green authored Jul 14, 2022
  3e0bf1c7
- [CommandLine] --help: print "-o <xxx>" instead of "-o=<xxx>" · 52cb9725
  Fangrui Song authored Jul 14, 2022
  52cb9725
- Revert "[llvm] add zstd to llvm::compression namespace" · 6e6be5f9
  Amara Emerson authored Jul 14, 2022
  6e6be5f9
- [SCCP] Don't check for UndefValue before calling markConstant() · 6db3edc8
  Nikita Popov authored Jun 22, 2022
  6db3edc8
- [AMDGPU] SIMachineScheduler: Add support for several MachineScheduler features · e5c4cde4
  Jannik Silvanus authored May 20, 2022
  e5c4cde4
- [llvm] Use value instead of getValue (NFC) · 611ffcf4
  Kazu Hirata authored Jul 13, 2022
  
  611ffcf4