Commits · d8f99bb6e0641474b6bc1728295b40a8fa279f9a · Roger Ferrer / llvm-epi · GitLab

Feb 11, 2022
- [AMDGPU] replace hostcall module flag with function attribute · d8f99bb6
  Sameer Sahasrabuddhe authored Feb 11, 2022
  d8f99bb6
- [AMDGPU] Add a new intrinsic to control fp_trunc rounding mode · dcb2da13
  Julien Pages authored Feb 11, 2022
  dcb2da13
- [SystemZ/z/OS] Add alias for XPLINK return · ff99f3a5
  Kai Nacke authored Feb 11, 2022
  ff99f3a5
- [X86] Move combineToExtendBoolVectorInReg before the select combines. NFC. · 48e1434a
  Simon Pilgrim authored Feb 11, 2022
  48e1434a
- [X86] combineToExtendBoolVectorInReg - use explicit arguments. NFC. · 827d0c51
  Simon Pilgrim authored Feb 11, 2022
  827d0c51
- [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics. · d224be3b
  Zakk Chen authored Feb 11, 2022
  d224be3b
- [AArch64][SVE] Fix selection failure caused by fp/int convert using non-Neon types · c53ad72a
  Bradley Smith authored Feb 10, 2022
  c53ad72a
- [AMDGPU][GlobalISel] Fix insert point in FoldableFneg combine · 5ff35ba8
  Mirko Brkusanin authored Feb 11, 2022
  5ff35ba8
- [M68k] Add missing include · 37bd80cd
  Simon Pilgrim authored Feb 11, 2022
  37bd80cd
- Cleanup MCParser headers · 06943537
  serge-sans-paille authored Feb 09, 2022
  06943537
- [AArch64] Emit TBAA metadata for SVE load/store intrinsics · 0b41238a
  Sander de Smalen authored Feb 11, 2022
  0b41238a
- [AArch64] Add a special case for shifting by (BitWidth - 1) - X · b21f497a
  Jay Foad authored Mar 31, 2020
  b21f497a
- [LoongArch] Include missing header files after D119244 · 1e8ff9b4
  Weining Lu authored Feb 11, 2022
  1e8ff9b4
- [X86] Zero out the 32-bit GPRs explicitly · 74aa44a8
  Bill Wendling authored Feb 10, 2022
  74aa44a8
- [RISCV] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds · 8eb75018
  Fangrui Song authored Feb 10, 2022
  
  8eb75018
- [AVR] Fix a potential assert failure · fa2d31e9
  Ben Shi authored Feb 10, 2022
  fa2d31e9
- Reland "[clang-cl] Support the /JMC flag" · f9270214
  Yuanfang Chen authored Feb 10, 2022
  f9270214
Feb 10, 2022
- [AMDGPU] Improve clobbering checks in the kernel argument promotion · 290e5722
  Stanislav Mekhanoshin authored Feb 10, 2022
  290e5722
- Revert "[clang-cl] Support the /JMC flag" · b380a31d
  Yuanfang Chen authored Feb 10, 2022
  b380a31d
- [TTI][X86] Pull out repeated getSizeInBits() calls. NFC. · 8c82d42e
  Simon Pilgrim authored Feb 10, 2022
  
  8c82d42e
- [clang-cl] Support the /JMC flag · bd3a1de6
  Yuanfang Chen authored Feb 10, 2022
  bd3a1de6
- [AArch64][LoadStoreOptimizer] Ignore undef registers when checking rename... · 1d74b531
  Huihui Zhang authored Feb 10, 2022
  1d74b531
- [RISCV] Lower the shufflevector equivalent of vector.splice · b0e77d5e
  Craig Topper authored Feb 10, 2022
  b0e77d5e
- [RISCV] Move the creation of VLMaxSentinel to isel. Use X0 during lowering. · b861ddf3
  Craig Topper authored Feb 10, 2022
  b861ddf3
- [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED. · 02e0d50e
  Paul Walker authored Feb 09, 2022
  02e0d50e
- [X86] getFMA3OpcodeToCommuteOperands - use unreachable to detect fma3 format mismatch · e95fc20f
  Simon Pilgrim authored Feb 10, 2022
  e95fc20f
- [RISCV] Remove stale comment. NFC · 727cd520
  Craig Topper authored Feb 10, 2022
  727cd520
- [DebugInfo][InstrRef] Avoid duplicate instruction numbers in x86-lea-fixup · 662799c8
  Jeremy Morse authored Feb 10, 2022
  662799c8
- [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection · d88a146f
  alex-t authored Feb 09, 2022
  d88a146f
- [AMDGPU] Pull out repeated getVecSize() calls. NFC. · 8de72973
  Simon Pilgrim authored Feb 10, 2022
  8de72973
- [AArch64] Improve codegen for get.active.lane.mask when SVE is available · 8b58494c
  David Sherwood authored Jan 05, 2022
  8b58494c
- [AMDGPU] Rename DSAtomicCmpXChg to DSAtomicCmpXChgSwapped. NFC. · e34623b1
  Jay Foad authored Feb 10, 2022
  e34623b1
- [SVE] Remove redundant hasBF16 calls from lowering code. · 9cc7eb0e
  Paul Walker authored Feb 08, 2022
  9cc7eb0e
- [SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD. · c58be857
  Paul Walker authored Feb 08, 2022
  c58be857
- [SVE][CodeGen] Bail out for scalable vectors in AArch64TargetLowering::ReconstructShuffle · a57a7f3d
  David Sherwood authored Jan 04, 2022
  a57a7f3d
- [AArch64][SVE] Fix selection failure during lowering of shuffle_vector · 98936aee
  Bradley Smith authored Feb 08, 2022
  98936aee
- [NVPTX] Use align attribute for kernel pointer arg alignment · 1c729d71
  Nikita Popov authored Feb 08, 2022
  1c729d71
- [LoongArch 4/6] Add basic tablegen infra for LoongArch · 33388ae8
  Lu Weining authored Feb 10, 2022
  33388ae8
- [LoongArch 3/6] Add target stub for LoongArch · 444c6d26
  Lu Weining authored Feb 10, 2022
  444c6d26
- [RISCV] Pre-process FP SPLAT_VECTOR to RISCVISD::VFMV_V_F_VL · fd43d99c
  Fraser Cormack authored Jan 19, 2022
  fd43d99c