Commits · d99260641b30b0638c6a1e60bcb971ec09fa5368 · Roger Ferrer / llvm-epi · GitLab

Aug 03, 2021
- [InstCombine] Fold phi ( inttoptr/ptrtoint x ) to phi (x) · d9926064
  Krishna authored Aug 02, 2021
  d9926064
- [InstCombine] Remove nnan requirement for transformation to fabs from select · 6180ce2e
  Krishna authored Aug 02, 2021
  6180ce2e
- [RISCV] Support simple fractional steps in matching VID sequences · cba6aab9
  Fraser Cormack authored Jul 16, 2021
  cba6aab9
- [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted · 0d8cd4e2
  Jason Molenda authored Aug 03, 2021
  0d8cd4e2
- [llvm-readobj][XCOFF] Fix the error dumping for the first · 69396896
  Esme-Yi authored Aug 03, 2021
  69396896
- [NFC] Rename enable-strict-reductions to force-ordered-reductions · 0156f91f
  David Sherwood authored Aug 02, 2021
  0156f91f
- [AMDGPU] Legalize operands of V_ADDC_U32_e32 and friends · 40202b13
  Jay Foad authored Jul 27, 2021
  40202b13
- Reland: "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes" · d3a0a65b
  Paulo Matos authored Jul 28, 2021
  d3a0a65b
- [RISCV] Teach VSETVLI insertion to merge the unused VSETVLI with the one need... · 7900ee0b
  Jianjian GUAN authored Aug 03, 2021
  7900ee0b
- [RISCV][test] Precommit tests for VSETVLI insertion improvement (D106857). · ed804588
  Jianjian GUAN authored Aug 03, 2021
  ed804588
- [RuntimeDyldChecker] Support offset in decode_operand expr · f4e418ac
  luxufan authored Aug 02, 2021
  f4e418ac
- [GlobalOpt] Fix the assert for stored once non-pointer to global address · 7ce98cf5
  Shimin Cui authored Aug 02, 2021
  7ce98cf5
- [AArch64][SelectionDAG] Support passing/returning scalable vectors with unusual types. · 1f62af63
  Eli Friedman authored Aug 02, 2021
  1f62af63
Aug 02, 2021
- [BasicTTIImpl][LoopUnroll] getUnrollingPreferences(): emit ORE remark when... · 6f6e9a86
  Roman Lebedev authored Aug 03, 2021
  6f6e9a86
- [InstCombine] `vector_reduce_{or,and}(?ext(<n x i1>))` -->... · 4ba3326f
  Roman Lebedev authored Aug 03, 2021
  4ba3326f
- [NFC][InstCombine] Add tests for or reduction w/ i1 element type (PR51259) · cdb0dfdf
  Roman Lebedev authored Aug 03, 2021
  
  cdb0dfdf
- [NFC][InstCombine] Add tests for and reduction w/ i1 element type (PR51259) · a2244933
  Roman Lebedev authored Aug 03, 2021
  
  a2244933
- [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress · bd13c8e6
  Jessica Paquette authored Aug 02, 2021
  bd13c8e6
- [InstCombine] `vector_reduce_smax(?ext(<n x i1>))` -->... · 554fc9ad
  Roman Lebedev authored Aug 03, 2021
  554fc9ad
- [NFC][InstCombine] Add tests for smax reduction w/ i1 element type (PR51259) · d7482a2b
  Roman Lebedev authored Aug 03, 2021
  
  d7482a2b
- [InstCombine] `vector_reduce_smin(?ext(<n x i1>))` -->... · f47b7b6d
  Roman Lebedev authored Aug 02, 2021
  f47b7b6d
- [NFC][InstCombine] Add tests for smin reduction w/ i1 element type (PR51259) · 4551a418
  Roman Lebedev authored Aug 02, 2021
  
  4551a418
- [AArch64] Regenerate fp16 tests. · 739efad3
  Eli Friedman authored Aug 02, 2021
  
  739efad3
- [InstCombine] `vector_reduce_umax(?ext(<n x i1>))` --> `?ext(vector_reduce_or(<n x i1>))` (PR51259) · b9b7162b
  Roman Lebedev authored Aug 02, 2021
  b9b7162b
- [NFC][InstCombine] Add tests for umax reduction w/ i1 element type (PR51259) · 9d179ee3
  Roman Lebedev authored Aug 02, 2021
  
  9d179ee3
- [InstCombine] `vector_reduce_umin(?ext(<n x i1>))` -->... · 0c137980
  Roman Lebedev authored Aug 02, 2021
  0c137980
- [NFC][InstCombine] Add tests for umin reduction w/ i1 element type (PR51259) · 7888cfe7
  Roman Lebedev authored Aug 02, 2021
  
  7888cfe7
- [SLP][X86] Add fmuladd test coverage · 317d70ea
  Simon Pilgrim authored Aug 02, 2021
  
  317d70ea
- [InstCombine] `vector_reduce_mul(?ext(<n x i1>))` --> `zext(vector_reduce_and(<n x i1>))` (PR51259) · 469793ef
  Roman Lebedev authored Aug 02, 2021
  469793ef
- [NFC][InstCombine] Add tests for mul reduction w/ i1 element type (PR51259) · 8baea415
  Roman Lebedev authored Aug 02, 2021
  
  8baea415
- Revert "[WebAssembly] Add new pass to lower int/ptr conversions of reftypes" · 245f2ee6
  Paulo Matos authored Aug 02, 2021
  245f2ee6
- [DWARF] Don't process .debug_info relocations for DWO Context · 5a865b0b
  Alexander Yermolovich authored Aug 02, 2021
  5a865b0b
- [WebAssembly] Add new pass to lower int/ptr conversions of reftypes · ce1c59de
  Paulo Matos authored Jul 28, 2021
  ce1c59de
- [VPlan] Use defined and ops VPValues to print VPInterleaveRecipe. · bb725c98
  Florian Hahn authored Aug 02, 2021
  bb725c98
- [InstCombine] `xor` reduction w/ i1 elt type is a parity check · 1e801439
  Roman Lebedev authored Aug 02, 2021
  1e801439
- [NFC][InstCombine] Add tests for xor reductions on i1 elt type (PR51259) · f6c44cdd
  Roman Lebedev authored Aug 02, 2021
  
  f6c44cdd
- [WebAssembly] Compute known bits for SIMD bitmask intrinsics · 417e5006
  Thomas Lively authored Aug 02, 2021
  417e5006
- [AArch64] Add shufflevector concat codegen tests. NFC. · ea23f7fc
  Sjoerd Meijer authored Aug 02, 2021
  
  ea23f7fc
- [VectorCombine] Fix PR30986 poison test case · f10d4cfc
  Simon Pilgrim authored Aug 02, 2021
  f10d4cfc
- [AArch64] Optimise min/max lowering in ISel · b01417d3
  Irina Dobrescu authored Jul 22, 2021
  b01417d3