Commits · da02ecb302c1b42a14c59921da0bb78cd647697c · Roger Ferrer / llvm-epi · GitLab

Dec 08, 2022
- [NFC] Port all BlockExtractor tests to `-passes=` syntax · da02ecb3
  Roman Lebedev authored Dec 08, 2022
  
  da02ecb3
- [NFC] Port all Attributor tests to `-passes=` syntax · f3a25957
  Roman Lebedev authored Dec 08, 2022
  
  f3a25957
- [NFC] Port all ArgumentPromotion tests to `-passes=` syntax · 679eaeb2
  Roman Lebedev authored Dec 08, 2022
  
  679eaeb2
- [NFC] Port all ADCE tests to `-passes=` syntax · 8f92fe83
  Roman Lebedev authored Dec 08, 2022
  
  8f92fe83
- [Bitcode(Reader|Writer)] Convert Optional to std::optional · 49e75ebd
  Krzysztof Parzyszek authored Dec 07, 2022
  
  49e75ebd
Dec 07, 2022
- [AMDGPU] Annotate the intrinsics to be default and nocallback · f6e3a89c
  Johannes Doerfert authored Oct 04, 2022
  f6e3a89c
- [amdgpu] Reimplement LDS lowering · d77ae7f2
  Jon Chesterfield authored Dec 07, 2022
  d77ae7f2
- [llvm-exegesis][x86] Add test coverage for Issue #38507 · 7bb16b02
  Simon Pilgrim authored Dec 07, 2022
  7bb16b02
- Generate DXIL Shader hash · c861ea87
  Chris Bieneman authored Dec 05, 2022
  c861ea87
- Revert "[llvm][dwwarf] Change CU/TU index to 64-bit" · f2f8f709
  Alexander Yermolovich authored Dec 07, 2022
  f2f8f709
- Revert "[DWARFLibrary] Add support to re-construct cu-index" · a7737647
  Alexander Yermolovich authored Dec 07, 2022
  a7737647
- [DWARFLibrary] Add support to re-construct cu-index · a5bd76a6
  Alexander Yermolovich authored Dec 06, 2022
  a5bd76a6
- [llvm][dwwarf] Change CU/TU index to 64-bit · 5ebd28f3
  Alexander Yermolovich authored Dec 05, 2022
  5ebd28f3
- Revert "[RISCV] Return InstSeq from generateInstSeqImpl instead of using an output parameter. NFC" · 2c52d516
  Craig Topper authored Dec 07, 2022
  2c52d516
- NVPTX: Cleanup check for denormal mode · 90f60a6a
  Matt Arsenault authored Dec 06, 2022
  90f60a6a
- AMDGPU: Rename test functions and add some cases for consistency · 5460b455
  Matt Arsenault authored Dec 06, 2022
  5460b455
- GISel/Combiner: maintain created instructions in a SetVector · 1598dc84
  Nicolai Hähnle authored Dec 01, 2022
  1598dc84
- [SPARC] Lower SELECT_CC to MOVr on 64-bit target whenever possible · f8f41c3f
  Koakuma authored Dec 07, 2022
  f8f41c3f
- [NFC][Object] Include header `BitcodeReader.h` instead of using forward... · 7ec057ff
  Shilei Tian authored Dec 07, 2022
  7ec057ff
- Revert "[SPARC] Mark the %g0 register as constant & use it to materialize zeros" · 7806f86a
  Brad Smith authored Dec 07, 2022
  7806f86a
- [RISCV] Without Zfh, promote f16 inputs before creating RISCVISD::FCVT_W(U)_RV64 nodes. · 258bb453
  Craig Topper authored Dec 07, 2022
  258bb453
- [NFC] Port all SimpleLoopUnswitch tests to `-passes=` syntax · 92e54b09
  Roman Lebedev authored Dec 07, 2022
  
  92e54b09
- [NFC] Port all (but one) HotColdSplit tests to `-passes=` syntax · 4d211ac8
  Roman Lebedev authored Dec 07, 2022
  
  4d211ac8
- [NFC] Port all CodeExtractor tests to `-passes=` syntax · 0ca8ddd8
  Roman Lebedev authored Dec 07, 2022
  
  0ca8ddd8
- [NFC] Port all LoopIdiom tests to `-passes=` syntax · 48c6b272
  Roman Lebedev authored Dec 07, 2022
  
  48c6b272
- [gn build] Reformat all build files · e5371e80
  Nico Weber authored Dec 07, 2022
  e5371e80
- [RISCV] Promote f16 fp_to_int_sat with Zfhmin during lowering instead of isel. · e3540fb9
  Craig Topper authored Dec 07, 2022
  e3540fb9
- [SPARC] Simplify instruction decoder. · 09900197
  James Y Knight authored Nov 20, 2022
  09900197
- [TableGen] More named sub-operands work. · 372240df
  James Y Knight authored Nov 08, 2022
  372240df
- [RISCV] Consolidate identical (fcopysign FPR32:, FPR16:) isel patterns. NFC · b12fe0d4
  Craig Topper authored Dec 07, 2022
  
  b12fe0d4
- Fix @llvm.global_ctors docs (NFC) · c9b6d641
  Keith Smiley authored Dec 07, 2022
  
  c9b6d641
- [NFC] Port all IndVarSimplify tests to `-passes=` syntax · 6017d9a6
  Roman Lebedev authored Dec 07, 2022
  
  6017d9a6
- [NFC] Port all RewriteStatepointsForGC tests to `-passes=` syntax · dcd5f6f2
  Roman Lebedev authored Dec 07, 2022
  
  dcd5f6f2
- [NFC] Port all MergeFunc tests to `-passes=` syntax · f38f99bd
  Roman Lebedev authored Dec 07, 2022
  
  f38f99bd
- [NFC] Port all GVN tests to `-passes=` syntax · 0aeedf58
  Roman Lebedev authored Dec 07, 2022
  
  0aeedf58
- [NFC] Port all IROutliner tests to `-passes=` syntax · 9dd9575c
  Roman Lebedev authored Dec 07, 2022
  
  9dd9575c
- AArch64: emit `fcmp ord %a, zeroinitializer` as a single fcmeq. · 6b98824a
  Tim Northover authored Nov 10, 2022
  6b98824a
- [NFC] Port all SLPVectorizer tests to `-passes=` syntax · 6697140b
  Roman Lebedev authored Dec 07, 2022
  
  6697140b
- [SPARC] Mark the %g0 register as constant & use it to materialize zeros · 2c41310f
  Koakuma authored Dec 07, 2022
  2c41310f
- [AMDGPU] Enable OMod on more VOP3 instructions · bbfbec94
  Joe Nash authored Dec 02, 2022
  bbfbec94