Commits · da1dfecd32f405d00b2432acd9fdd24526e5614f · Roger Ferrer / llvm-epi · GitLab

Jul 03, 2019
- [X86] Add a DAG combine for turning *_extend_vector_inreg+load into an... · b770d2c9
  Craig Topper authored Jul 02, 2019
  b770d2c9
Jul 02, 2019
- [ARM] Fix unwind info for Thumb1 functions that save high registers. · e97aa961
  Eli Friedman authored Jul 02, 2019
  e97aa961
- [AArch64][GlobalISel] Teach tryOptSelect to handle G_ICMP · 99316043
  Jessica Paquette authored Jul 02, 2019
  99316043
- AMDGPU: Custom lower vector_shuffle for v4i16/v4f16 · 5fe851b6
  Matt Arsenault authored Jul 02, 2019
  5fe851b6
- [X86] getTargetConstantBitsFromNode - remove unnecessary getZExtValue() (PR42486) · 56138749
  Simon Pilgrim authored Jul 02, 2019
  56138749
- [AMDGPU] LCSSA pass added in preISel. Fixing typo in previous commit · 66ac6b40
  Alexander Timofeev authored Jul 02, 2019
  66ac6b40
- [AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent loop and used outside · 2ce560f0
  Alexander Timofeev authored Jul 02, 2019
  2ce560f0
- [X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm... · cffbaa93
  Craig Topper authored Jul 02, 2019
  cffbaa93
- AMDGPU/GlobalISel: Try generated matcher with intrinsics · 50be3481
  Matt Arsenault authored Jul 02, 2019
  50be3481
- AMDGPU/GlobalISel: Select mul · a8bff4b9
  Matt Arsenault authored Jul 02, 2019
  a8bff4b9
- AMDGPU/GlobalISel: Fix G_GEP with mixed SGPR/VGPR operands · 70a4d3f6
  Matt Arsenault authored Jul 02, 2019
  70a4d3f6
- AMDGPU/GlobalISel: Select G_FENCE · ed633992
  Matt Arsenault authored Jul 02, 2019
  ed633992
- [X86][AVX] combineX86ShuffleChain - pull out CombineShuffleWithExtract lambda. NFCI. · 93041681
  Simon Pilgrim authored Jul 02, 2019
  93041681
- [ARM] MVE: allow soft-float ABI to pass vector types. · bffd099d
  Simon Tatham authored Jul 02, 2019
  bffd099d
- [ARM] Stop using scalar FP instructions in integer-only MVE mode. · 7b63a953
  Simon Tatham authored Jul 02, 2019
  7b63a953
- [X86] resolveTargetShuffleInputsAndMask - add repeated input handling. · d609ebb7
  Simon Pilgrim authored Jul 02, 2019
  d609ebb7
- [mips] Mark P5600 scheduling model as complete · 1d7d0e21
  Simon Atanasyan authored Jul 02, 2019
  1d7d0e21
- [mips] Add missing schedinfo for FPU load/store/conv instructions · f2867518
  Simon Atanasyan authored Jul 02, 2019
  f2867518
- [mips] Map SNOP, NOP to the P5600Nop scheduler resource · 116cf95c
  Simon Atanasyan authored Jul 02, 2019
  116cf95c
- [X86] Add PreprocessISelDAG support for turning ISD::FP_TO_SINT/UINT into... · 2d306b2d
  Craig Topper authored Jul 02, 2019
  2d306b2d
- [PowerPC] Implement the areMemAccessesTriviallyDisjoint hook · 7fdb3a29
  QingShan Zhang authored Jul 02, 2019
  7fdb3a29
- Revert Recommit [PowerPC] Update P9 vector costs for insert/extract element · 351b7e7b
  Jordan Rupprecht authored Jul 01, 2019
  351b7e7b
- AMDGPU: Correct properties for adjcallstack* pseudos · 40c08052
  Matt Arsenault authored Jul 01, 2019
  40c08052
Jul 01, 2019
- [X86] Use v4i32 vzloads instead of v2i64 for vpmovzx/vpmovsx patterns where... · 3f722d40
  Craig Topper authored Jul 01, 2019
  3f722d40
- [mips] Add missing schedinfo for MIPSeh_return[32|64] instructions · fa275006
  Simon Atanasyan authored Jul 01, 2019
  fa275006
- [mips] Add virtualization ASE to P5600 scheduling definitions · 29801f78
  Simon Atanasyan authored Jul 01, 2019
  29801f78
- [mips] Add missing schedinfo for LONG_BRANCH_* instructions · 574d0a61
  Simon Atanasyan authored Jul 01, 2019
  574d0a61
- [X86] Remove several bad load folding isel patterns for VPMOVZX/VPMOVSX. · 328b2415
  Craig Topper authored Jul 01, 2019
  328b2415
- [X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns · 5e7815b6
  Craig Topper authored Jul 01, 2019
  5e7815b6
- AMDGPU/GlobalISel: Handle more input argument intrinsics · bae3636f
  Matt Arsenault authored Jul 01, 2019
  bae3636f
- AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics · 9e8e8c60
  Matt Arsenault authored Jul 01, 2019
  9e8e8c60
- AMDGPU/GlobalISel: Legalize workgroup ID intrinsics · 756d8190
  Matt Arsenault authored Jul 01, 2019
  756d8190
- AMDGPU/GlobalISel: Legalize workitem ID intrinsics · e2c86cce
  Matt Arsenault authored Jul 01, 2019
  e2c86cce
- AMDGPU/GlobalISel: Custom lower control flow intrinsics · e15770ae
  Matt Arsenault authored Jul 01, 2019
  e15770ae
- AMDGPU/GlobalISel: Handle 16-bit SALU min/max · 4073b337
  Matt Arsenault authored Jul 01, 2019
  4073b337
- AMDGPU/GlobalISel: Lower SALU min/max to cmp+select · 5a7d5111
  Matt Arsenault authored Jul 01, 2019
  5a7d5111
- [X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2) · e20030f6
  Robert Lougher authored Jul 01, 2019
  e20030f6
- AMDGPU/GlobalISel: Legalize s16 add/sub/mul · ef59cb69
  Matt Arsenault authored Jul 01, 2019
  ef59cb69
- AMDGPU/GlobalISel: Fix allowing non-boolean conditions for G_SELECT · 9470bb26
  Matt Arsenault authored Jul 01, 2019
  9470bb26
- AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghalt · b2ea20ee
  Matt Arsenault authored Jul 01, 2019
  b2ea20ee