Commits · da59fe7f15f5fbf84fd26a89096e88fc0453f48e · Roger Ferrer / llvm-epi · GitLab

Sep 12, 2022
- AMDGPU: Fix test failure · da59fe7f
  Matt Arsenault authored Sep 12, 2022
  da59fe7f
- RegAllocGreedy: Try local instruction splitting with subranges · e3027116
  Matt Arsenault authored Jul 24, 2022
  e3027116
- CodeGen: Set MODereferenceable from isDereferenceableAndAlignedPointer · bb70b5d4
  Matt Arsenault authored Jul 18, 2022
  bb70b5d4
- DeadMachineInstructionElim: Switch to using LiveRegUnits · b5041527
  Matt Arsenault authored Apr 21, 2022
  b5041527
- [AArch64] Add some extra typepromotion cost tests. NFC · f072263e
  David Green authored Sep 12, 2022
  
  f072263e
- [llvm][AArch64] Test warning for clobbering w19 with base frame pointer · 29bb6497
  David Spickett authored Sep 12, 2022
  29bb6497
- [LLVM][AArch64] Explain that X19 is used as the frame base pointer register · 739b69e6
  David Spickett authored Sep 02, 2022
  739b69e6
Sep 10, 2022
- [DAGCombiner] Use HandleSDNode to keep node alive across call to getNegatedExpression. · 545affbf
  Craig Topper authored Sep 09, 2022
  545affbf
Sep 09, 2022
- [AArch64][CodeGen]Fold the mov and lsl into ubfiz · 7a817825
  zhongyunde authored Sep 09, 2022
  7a817825
- [AMDGPU] Fix crash legalizing G_EXTRACT_VECTOR_ELT with negative index · 8901f7ce
  Jay Foad authored Aug 30, 2022
  8901f7ce
- [NFC][AMDGPU] Pre-commit test for D132837. · 72730c3f
  Thomas Symalla authored Sep 09, 2022
  
  72730c3f
- [LoongArch] Add codegen support for frint · da8c9521
  gonglingqin authored Sep 09, 2022
  da8c9521
- [DAGCombiner][X86] Fold (sub (subcarry X, 0, Carry), Y) -> (subcarry X, Y, Carry) · aa83bdd1
  Craig Topper authored Sep 08, 2022
  aa83bdd1
- [RISCV] Add the GlobalMerge pass (disabled by default) · 51ae4624
  Alex Bradbury authored Sep 08, 2022
  51ae4624
- [Peephole] rewrite INSERT_SUBREG to SUBREG_TO_REG if upper bits zero · b6655333
  zhongyunde authored Sep 09, 2022
  b6655333
Sep 08, 2022
- [ARM] Add tests on instructions fusion with comparison with zero; NFC · c4d0509e
  Filipp Zhinkin authored Sep 08, 2022
  c4d0509e
- [AArch64] Add test for vscale nontemporal loads larger than 256. · 04548e82
  Zain Jaffal authored Sep 08, 2022
  04548e82
- [AMDGPU] Fix shrinking of F16 FMA on newer subtargets · afa0ed33
  Jay Foad authored Sep 08, 2022
  afa0ed33
- [SystemZ] Improve handling of vector alignments. · de0e3117
  Jonas Paulsson authored Aug 04, 2022
  de0e3117
- [WebAssembly] Prototype `f32x4.relaxed_dot_bf16x8_add_f32` · ac3b8df8
  Thomas Lively authored Sep 08, 2022
  ac3b8df8
- [Hexagon] Handle shifts of short vectors of i8 · 3c817574
  Krzysztof Parzyszek authored Sep 08, 2022
  
  3c817574
- [NFC][Regalloc] Introduce the RegAllocPriorityAdvisorAnalysis · d8a2d3f7
  Eric Wang authored Sep 07, 2022
  d8a2d3f7
- [AArch64] Add tests for lowering trunc to i8 using tbl. · 39fcb4a2
  Florian Hahn authored Sep 08, 2022
  
  39fcb4a2
- [AMDGPU] Only raise wave priority if there is a long enough sequence of VALU instructions. · 57c943d5
  Ivan Kosarev authored Sep 08, 2022
  57c943d5
- [AMDGPU] Add basic tests for emitting v_fma_f16 and friends · 5b652f77
  Jay Foad authored Sep 08, 2022
  
  5b652f77
- [AArch64] Add tests for shuffle (tbl2, tbl2) -> tbl4 fold. · 7d4ee326
  Florian Hahn authored Sep 08, 2022
  7d4ee326
- [AArch64][SVE] Add out of range SVE arg CC test · 3864643d
  Matt Devereau authored Sep 08, 2022
  3864643d
- [AARCH64][COST] Improve cost of reverse shuffles for AArch64 · 723245bf
  liqinweng authored Sep 08, 2022
  723245bf
- [AArch64] add i56 load store pair test case; NFC · 5b5f6e75
  chenglin.bi authored Sep 08, 2022
  
  5b5f6e75
- [ConstantExpr] Remove fneg expression · 96cb7c22
  Nikita Popov authored Sep 07, 2022
  96cb7c22
- [LoongArch] Add codegen support for atomicrmw xchg operation on LA32 · d5f7a218
  gonglingqin authored Sep 08, 2022
  d5f7a218
- [LoongArch] Add codegen support for atomicrmw xchg operation on LA64 · b60f8016
  gonglingqin authored Jul 19, 2022
  b60f8016
- [X86] Pre-commit test for PR57576. NFC · 7c99bf80
  Craig Topper authored Sep 07, 2022
  
  7c99bf80
- [AMDGPU] Drop _oneuse checks from med3 patterns · a81c7dbf
  Justin Bogner authored Aug 24, 2022
  a81c7dbf
- [AMDGPU] Fix liveness verifier error in hazard recognizer · fb28bf3f
  Stanislav Mekhanoshin authored Sep 07, 2022
  fb28bf3f
Sep 07, 2022
- [AMDGPU] W/a hazard if 64 bit shift amount is a highest allocated VGPR · 95d497ff
  Stanislav Mekhanoshin authored Aug 31, 2022
  95d497ff
- [AArch64] Add tests for using tbl for fp conversions. · 8105f555
  Florian Hahn authored Sep 07, 2022
  
  8105f555
- [amdgpu] Always, instead of mostly, remove unused LDS symbols · 23f6c8d6
  Jon Chesterfield authored Sep 07, 2022
  23f6c8d6
- [AArch64] Add additional tests for tbl expansion. · faf9e050
  Florian Hahn authored Sep 07, 2022
  faf9e050
- [RISCV][MC] Add minimal support for Ztso extension · a4a29438
  Philip Reames authored Sep 07, 2022
  a4a29438