Commits · db4ac5a63e11b90ab585abf9531edb4ed6f69be0 · Roger Ferrer / llvm-epi · GitLab

Jun 08, 2021
- [RISCV] Remove dead code from fixed-vectors-abs.ll test cases. NFC · c09b3755
  Craig Topper authored Jun 08, 2021
  c09b3755
- Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. · 8b4c80d3
  Craig Topper authored Jun 08, 2021
  8b4c80d3
- [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions. · c57bce9c
  Craig Topper authored Jun 08, 2021
  c57bce9c
- [RISCV] Add a test case showing inefficient vector codegen · ccd1e087
  Fraser Cormack authored Jun 08, 2021
  
  ccd1e087
- [DAG] Allow isNullOrNullSplat to see truncated zeroes · b889c6ee
  David Green authored Jun 08, 2021
  b889c6ee
- [RISCV] Use 0 for Log2SEW for vle1/vse1 intrinsics to enable vsetvli optimization. · 7c4e9a68
  Craig Topper authored Jun 07, 2021
  7c4e9a68
- [RISCV] Masked compares should use a tail agnostic policy. · ae3ab4f0
  Craig Topper authored Jun 07, 2021
  ae3ab4f0
- [RISCV] Optimize bitwise and with constant for the Zbs extension · c705b7b0
  Ben Shi authored Jun 08, 2021
  c705b7b0
Jun 07, 2021
- [RISCV] Lower i8/i16 bswap/bitreverse to grevi/greviw with Zbp. · f30f8b4f
  Craig Topper authored Jun 07, 2021
  f30f8b4f
Jun 04, 2021
- [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. · c653711f
  Craig Topper authored Jun 04, 2021
  c653711f
- [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR · aec9cbbe
  Fraser Cormack authored May 27, 2021
  aec9cbbe
Jun 03, 2021
- [AtomicExpand] Merge cmpxchg success and failure ordering when appropriate. · 44cdf771
  Eli Friedman authored May 28, 2021
  44cdf771
- [RISCV] Precommit a test case to show overwriting vector frame objects. · 9d4922ea
  Hsiangkai Wang authored Jun 03, 2021
  
  9d4922ea
- [RISCV] Reserve an emergency spill slot for any RVV spills · 8790e852
  Fraser Cormack authored May 26, 2021
  8790e852
- [CodeGen] Fix a scalable-vector crash in VSELECT legalization · 1de1887f
  Fraser Cormack authored Jun 02, 2021
  1de1887f
- [ValueTypes] Fix scalable-vector changeExtendedVectorTypeToInteger · 2dd20a31
  Fraser Cormack authored Jun 02, 2021
  2dd20a31
Jun 02, 2021
- [RISCV][NFC] Add '+mattr=+experimental-v' to RVV test · 1cea1189
  Fraser Cormack authored Jun 02, 2021
  
  1cea1189
- [RISCV] Expand unaligned fixed-length vector memory accesses · 3b0a33d0
  Fraser Cormack authored May 14, 2021
  3b0a33d0
- [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. · 41ff1e0e
  Craig Topper authored Jun 01, 2021
  41ff1e0e
- [RISCV][test] Add new tests of bitwise and with constant for the Zbs extension · 59f44f9a
  Ben Shi authored May 29, 2021
  59f44f9a
Jun 01, 2021
- [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and... · 896f9bc3
  Craig Topper authored Jun 01, 2021
  896f9bc3
- [RISCV] Remove earlyclobber from compares with LMUL<=1. · 5a5219a0
  Craig Topper authored Jun 01, 2021
  5a5219a0
- [RISCV] Support vector types in combination with fastcc · 4f500c40
  Fraser Cormack authored May 13, 2021
  4f500c40
May 31, 2021
- [RISCV] Scale scalably-typed split argument offsets by VSCALE · 2b37c405
  Fraser Cormack authored May 27, 2021
  2b37c405
- [RISCV] Support vector conversions between fp and i1 · eb239365
  Fraser Cormack authored May 28, 2021
  eb239365
May 29, 2021
- Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" · 00dfd4f8
  Jessica Clarke authored May 29, 2021
  00dfd4f8
- [RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases · aa9a30b8
  Jessica Clarke authored May 29, 2021
  aa9a30b8
May 28, 2021
- [RISCV] Pre-commit test cases for D103211. NFC · a4130996
  Craig Topper authored May 28, 2021
  
  a4130996
- [AArch64][RISCV] Make sure isel correctly honors failure orderings. · 0b3b0a72
  Eli Friedman authored May 27, 2021
  0b3b0a72
- [RISCV][NFC] Merge identical RV32 and RV64 test checks · 3f5ae368
  Fraser Cormack authored May 28, 2021
  
  3f5ae368
- [RISCV] Add tests for fixed vector conversions between fp to/from i1 · f3afd0d1
  Fraser Cormack authored May 28, 2021
  f3afd0d1
- [RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli. · 0fa5aac2
  Craig Topper authored May 27, 2021
  0fa5aac2
May 27, 2021
- [RISCV] Fix typo, use addImm instead of addReg. · 020df692
  Craig Topper authored May 27, 2021
  
  020df692
- [RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop. · d7ae2438
  Craig Topper authored May 27, 2021
  d7ae2438
- [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell... · 527cd013
  Craig Topper authored May 27, 2021
  527cd013
- [RISCV] Add a test case showing incorrect call-conv lowering · 6f4794fe
  Fraser Cormack authored May 27, 2021
  6f4794fe
- [DAGCombine][RISCV] Don't try to trunc-store combined vector stores · b7101e21
  Fraser Cormack authored May 26, 2021
  b7101e21
- [RISCV] Allow passing fixed-length vectors via the stack · 8c73a31c
  Fraser Cormack authored May 13, 2021
  8c73a31c
- [SelectionDAG][RISCV] Don't unroll 0/1-type bool VSELECTs · 772b58a6
  Fraser Cormack authored May 26, 2021
  772b58a6
May 26, 2021
- [RISCV] Use X0 as destination of inserted vsetvli when possible. · fdf10e61
  Craig Topper authored May 26, 2021
  fdf10e61