Commits · dc25e1d8e2a76741b46a68a76f48c3c346a2fa40 · Roger Ferrer / llvm-epi · GitLab

Jan 17, 2018
- [LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization. · c60a23a6
  Eli Friedman authored Jan 17, 2018
  c60a23a6
- Revert [PowerPC] This reverts commit rL322721 · c9dc7b45
  Zaara Syeda authored Jan 17, 2018
  c9dc7b45
- [PowerPC] Add handling for ColdCC calling convention and a pass to mark · 8e951fd2
  Zaara Syeda authored Jan 17, 2018
  8e951fd2
Jan 12, 2018
- [PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate · 309124e0
  Benjamin Kramer authored Jan 12, 2018
  309124e0
- [PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP · ebb23078
  Nemanja Ivanovic authored Jan 12, 2018
  ebb23078
- Revert "[PowerPC] Manually schedule the prologue and epilogue" · 70bfe661
  Stefan Pintilie authored Jan 12, 2018
  70bfe661
Jan 10, 2018
- [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'. · fe6c9cbb
  Puyan Lotfi authored Jan 10, 2018
  fe6c9cbb
Jan 09, 2018
- [PowerPC] Manually schedule the prologue and epilogue · 17127008
  Stefan Pintilie authored Jan 09, 2018
  17127008
- [CodeGen] Don't print register classes in -debug output · 2b3bd306
  Francis Visoiu Mistrih authored Jan 09, 2018
  2b3bd306
- [PowerPC] Can not assume an intrinsic argument is a simple type. · 33a17762
  Sean Fertile authored Jan 09, 2018
  33a17762
- Revert "[PowerPC] Manually schedule the prologue and epilogue" · 7e10987b
  Stefan Pintilie authored Jan 09, 2018
  7e10987b
Jan 08, 2018
- [PowerPC] Manually schedule the prologue and epilogue · 55bfdd04
  Stefan Pintilie authored Jan 08, 2018
  55bfdd04
Dec 30, 2017
- [PowerPC] fix a bug in TCO eligibility check · ca3cdd7f
  Hiroshi Inoue authored Dec 30, 2017
  ca3cdd7f
Dec 29, 2017
- [PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion · 4e1f5e07
  Nemanja Ivanovic authored Dec 29, 2017
  4e1f5e07
Dec 28, 2017
- Unbreak test relying on debug output after r321540. · a19d42f9
  Benjamin Kramer authored Dec 28, 2017
  a19d42f9
Dec 22, 2017
- [SelectionDAG] Reverse the order of operands in the ISD::ADD created by... · b2368fbd
  Craig Topper authored Dec 22, 2017
  b2368fbd
Dec 21, 2017
- [PowerPC] Fix parest build failure in SPEC2017. · eba757e4
  Tony Jiang authored Dec 21, 2017
  eba757e4
Dec 20, 2017
- [PowerPC] fix a bug in redundant compare elimination · 11e571e0
  Hiroshi Inoue authored Dec 20, 2017
  11e571e0
Dec 18, 2017
- [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation. · efc7c88e
  Benjamin Kramer authored Dec 18, 2017
  efc7c88e
Dec 15, 2017
- [PowerPC] Convert r+r instructions to r+i (pre and post RA) · 6995e5da
  Nemanja Ivanovic authored Dec 15, 2017
  6995e5da
- Disabling r312514 as it causes miscompiles that show up on bootstrap · 0d47d32c
  Nemanja Ivanovic authored Dec 15, 2017
  0d47d32c
Dec 14, 2017
- [CodeGen] Print external symbols as $symbol in both MIR and debug output · e76c5fcd
  Francis Visoiu Mistrih authored Dec 14, 2017
  e76c5fcd
Dec 13, 2017
- [PowerPC] MachineSSA pass to reduce the number of CR-logical operations · 6f590bf8
  Nemanja Ivanovic authored Dec 13, 2017
  6f590bf8
Dec 12, 2017
- [MachineOperand][MIR] Add isRenamable to MachineOperand. · 60c43102
  Geoff Berry authored Dec 12, 2017
  60c43102
- [PowerPC] Follow-up to r318436 to get the missed CSE opportunities · b0783ccc
  Nemanja Ivanovic authored Dec 12, 2017
  b0783ccc
Dec 11, 2017
- [PowerPC] Partially enable the ISEL expansion pass. · 3b49dc54
  Tony Jiang authored Dec 11, 2017
  3b49dc54
- [PowerPC] Sign-extend negative constant stores · 50d37a11
  Nemanja Ivanovic authored Dec 11, 2017
  50d37a11
Dec 07, 2017
- Temporarily revert "[PowerPC] Allow tail calls of fastcc functions from C CallingConv functions." · a469acac
  Eric Christopher authored Dec 07, 2017
  a469acac
- [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. · a8a83d15
  Francis Visoiu Mistrih authored Dec 07, 2017
  a8a83d15
Dec 05, 2017
- Add REQUIRES asserts in combine_loads_from_build_pair.ll · 5abbad79
  Bjorn Pettersson authored Dec 05, 2017
  5abbad79
- [DAGCombine] Handle big endian correctly in CombineConsecutiveLoads · 823b299f
  Bjorn Pettersson authored Dec 05, 2017
  823b299f
Dec 04, 2017
- [CodeGen] Unify MBB reference format in both MIR and debug output · 25528d6d
  Francis Visoiu Mistrih authored Dec 04, 2017
  25528d6d
Dec 01, 2017
- Follow-up to r319434 to turn the pass on by default · 4364513c
  Nemanja Ivanovic authored Dec 01, 2017
  4364513c
Nov 30, 2017
- [CodeGen] Always use `printReg` to print registers in both MIR and debug · c71cced0
  Francis Visoiu Mistrih authored Nov 30, 2017
  c71cced0
- [PowerPC] Recommit r314244 with refactoring and off by default · db7e7704
  Nemanja Ivanovic authored Nov 30, 2017
  db7e7704
- [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output · 93ef1458
  Francis Visoiu Mistrih authored Nov 30, 2017
  93ef1458
- First step towards more human-friendly PPC assembler output: · 4b1acff9
  Joerg Sonnenberger authored Nov 29, 2017
  4b1acff9
Nov 29, 2017
- [Power9] add more tests for D38287; NFC · 76fe1006
  Zaara Syeda authored Nov 29, 2017
  76fe1006
- [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended. · aab3ef76
  Sean Fertile authored Nov 29, 2017
  aab3ef76
Nov 28, 2017
- [PowerPC] Allow tail calls of fastcc functions from C CallingConv functions. · e200016e
  Sean Fertile authored Nov 28, 2017
  e200016e