Commits · dcfc1fd26f6c2e6ecb1f8f9ae1b77d7b5c30c434 · Roger Ferrer / llvm-epi · GitLab

Jul 15, 2022
- [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. · dcfc1fd2
  Craig Topper authored Jul 14, 2022
  dcfc1fd2
- [RISCV] Add additional tests for D121833. NFC · 450f0bd1
  Craig Topper authored Jul 11, 2022
  
  450f0bd1
Jul 14, 2022
- [AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable. · 2e29b013
  Alexander Timofeev authored Jun 21, 2022
  2e29b013
- [GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT. · d4f84df0
  Amara Emerson authored Jul 14, 2022
  d4f84df0
- [RISCV] Add a RISCV specific CodeGenPrepare pass. · 1a8468ba
  Craig Topper authored Jul 14, 2022
  1a8468ba
- [MachineCombiner] Don't compute the latency of transient instructions · 2f11b3a6
  Guozhi Wei authored Jul 14, 2022
  2f11b3a6
- [RISCV] Disable subregister liveness by default · d1a5669f
  Fraser Cormack authored Jul 13, 2022
  d1a5669f
- Revert "[StructurizeCFG] Improve basic block ordering" · c945d88d
  Brendon Cahoon authored Jul 14, 2022
  c945d88d
- [RISCV] Add a test showing a miscompilation with subreg liveness · 3b334978
  Fraser Cormack authored Jul 13, 2022
  3b334978
- [NFC][SVE] Add tests for zext(cmpeq(x, splat(0))) · a2fe6aa9
  Cullen Rhodes authored Jul 14, 2022
  a2fe6aa9
- [LoongArch] Implement OR combination to generate bstrins.w/d · 9b87ad33
  Weining Lu authored Jul 13, 2022
  9b87ad33
- [GlobalISel] Re-generate some checks. · cef349a3
  Amara Emerson authored Jul 14, 2022
  
  cef349a3
- [BPF] Handle anon record for CO-RE relocations · 6e6c1efe
  Yonghong Song authored Jul 12, 2022
  6e6c1efe
Jul 13, 2022
- [GlobalISel] Fix and(load)->zextload combine crash. · 2824bdd9
  Amara Emerson authored Jul 13, 2022
  2824bdd9
- [RISCV] Fold (sra (sext_inreg (shl X, C1), i32), C2) -> (sra (shl X, C1+32), C2+32). · 25775553
  Craig Topper authored Jul 13, 2022
  25775553
- [RISCV] Add test case show missed opportunity to turn slliw+sraiw into slli+srai. · e32864b6
  Craig Topper authored Jul 13, 2022
  e32864b6
- [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u · 2ce0a5c8
  Alex Bradbury authored Jul 13, 2022
  2ce0a5c8
- [RISCV] Exploit fact that vscale is always power of two to replace urem sequence · dde2a7fb
  Philip Reames authored Jul 12, 2022
  dde2a7fb
- [DAG] SimplifyDemandedVectorElts - adjust demanded elements for selection mask... · d172842b
  Simon Pilgrim authored Jul 13, 2022
  d172842b
- [DAGCombine] fold (urem x, (lshr pow2, y)) -> (and x, (add (lshr pow2, y), -1)) · fd67992f
  Philip Reames authored Jul 12, 2022
  fd67992f
- [AArch64] Regenerate arm64-vshuffle.ll test checks · 04419a5f
  Simon Pilgrim authored Jul 13, 2022
  04419a5f
- [AArch64] Regenerate arm64-vselect.ll test checks · 9bc77b73
  Simon Pilgrim authored Jul 13, 2022
  9bc77b73
- [ARM] Regenerate select_xform.ll test checks · 5271fcd8
  Simon Pilgrim authored Jul 13, 2022
  
  5271fcd8
- [ARM] Fix subtarget features for Thumb2 tests. NFC · 6c46b3d6
  David Green authored Jul 13, 2022
  6c46b3d6
- [PowerPC] Regenerate pr35402.ll test checks · 64ffcba1
  Simon Pilgrim authored Jul 13, 2022
  
  64ffcba1
- [X86] Regenerate fp_constant_op.ll test checks · 79e18477
  Simon Pilgrim authored Jul 13, 2022
  
  79e18477
- [AIX] follow-up of D124654. · 100319cd
  esmeyi authored Jul 13, 2022
  100319cd
- [LoongArch] Add codegen support for atomic fence, atomic load and atomic store · 47f3dc6d
  gonglingqin authored Jul 13, 2022
  47f3dc6d
- [LoongArch] Add codegen support for converting between unsigned integer and floating-point · e147a0f6
  gonglingqin authored Jul 13, 2022
  e147a0f6
- [LoongArch] Add codegen support for fpround, fpextend and converting between... · 1df96ce5
  gonglingqin authored Jul 13, 2022
  1df96ce5
- [RISCV][test] Add test of binop followed by extractelement. · 9049c46b
  Jianjian GUAN authored Jul 12, 2022
  9049c46b
- Add coverage for missing (urem x, (lshr pow2, y)) -> (and x, (add (lshr pow2, y), -1)) transform · cc7d9665
  Philip Reames authored Jul 12, 2022
  
  cc7d9665
- {RISCV] Test coverage for improved lowering assuming vscale is pow-of-two · 1ce3f945
  Philip Reames authored Jul 12, 2022
  
  1ce3f945
Jul 12, 2022
- Revert "[GISel] Unify use of getStackGuard" · 4ae254e4
  Kai Nacke authored Jul 12, 2022
  4ae254e4
- [GISel] Unify use of getStackGuard · e60b4fb2
  Kai Nacke authored Jul 12, 2022
  e60b4fb2
- [AMDGPU] Regenerate local-memory.amdgcn.ll test checks · 42ca354c
  Simon Pilgrim authored Jul 12, 2022
  
  42ca354c
- [TargetLowering][RISCV] Make expandCTLZ work for non-power of 2 types. · 8eaf00e0
  Craig Topper authored Jul 09, 2022
  8eaf00e0
- [RISCV] Pre-commit test for PR56457. NFC · 866be0aa
  Craig Topper authored Jul 09, 2022
  
  866be0aa
- [X86] initial -mfunction-return=thunk-extern support · 2240d72f
  Nick Desaulniers authored Jul 12, 2022
  2240d72f
- [AMDGPU] SILowerControlFlow uses LiveIntervals · 5d41fe07
  Jay Foad authored Jul 12, 2022
  5d41fe07