Commits · dd0d36d09f39942df1e188d2df3a4f7dcc4b8245 · Roger Ferrer / llvm-epi · GitLab

Aug 21, 2023
- [RISCVInsertVSETVLI] Handle vl-preserve case in backwards rewrite · dd0d36d0
  Philip Reames authored Aug 21, 2023
  dd0d36d0
Aug 19, 2023
- [DAGCombiner] Don't reduce BUILD_VECTOR to BITCAST before LegalizeTypes if VT is legal. · 18f5ada2
  Jim Lin authored Aug 19, 2023
  18f5ada2
Aug 18, 2023
- [DAG] Restrict insert_subvector undef, splat_veector, dontcare transform · 92e0c0dc
  Philip Reames authored Aug 18, 2023
  92e0c0dc
- [DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types · 67b71ad0
  Philip Reames authored Aug 18, 2023
  67b71ad0
- Revert "[DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types" · bbbb93eb
  Craig Topper authored Aug 18, 2023
  bbbb93eb
- [DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types · 770be43f
  Craig Topper authored Aug 18, 2023
  770be43f
- [RISCV] Bump vector crypto to v1.0 RC2 · 29f11e4f
  4vtomat authored Aug 16, 2023
  29f11e4f
- [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion · 0816b3ef
  Kito Cheng authored Aug 18, 2023
  0816b3ef
- [RISCV] Precommit test for D158086 · b00b4697
  Kito Cheng authored Aug 18, 2023
  b00b4697
Aug 16, 2023
- [RISCVInsertVSETVLI] Generalize scalar extract (vmv.x.s, and vmx.f.s) hamdling · 3c2a6697
  Philip Reames authored Aug 16, 2023
  3c2a6697
- [RISCVInsertVSETVLI] Default to VL=1 for scalar extracts · b06e52c3
  Philip Reames authored Aug 16, 2023
  b06e52c3
- [SelectionDAG] Use TypeSize variant of ComputeValueVTs to compute correct... · 56606520
  Paul Walker authored Aug 14, 2023
  56606520
Aug 14, 2023
- [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands · a63bd7e9
  Philip Reames authored Aug 14, 2023
  a63bd7e9
- [RISCV] Lower reverse shuffles of fixed i1 vectors to vbrev.v · 9f369a4c
  Luke Lau authored Aug 10, 2023
  9f369a4c
- [LegalizeTypes] Factor in vscale_range when widening insert_subvector · 6238b8ea
  Luke Lau authored Aug 09, 2023
  6238b8ea
- [RISCV] Match ext + ext + srem + trunc to vrem.vv · 555e0305
  LWenH authored Aug 13, 2023
  555e0305
- [RISCV] Add Precommit test for D156685 · 6cb55a3d
  LWenH authored Aug 13, 2023
  6cb55a3d
- [RISCV] Truncate constants to EltSize when combine store of BUILD_VECTOR · 8a98f24e
  Pengcheng Wang authored Aug 14, 2023
  8a98f24e
Aug 12, 2023
- [RISCV] Add test coverage for matching strided loads with negative offsets · 84a2b55b
  Philip Reames authored Aug 11, 2023
  
  84a2b55b
Aug 11, 2023
- [LegalizeTypes] Support promotion for vp bitmanip sdnodes. · 69cc5a4e
  Yeting Kuo authored Aug 10, 2023
  69cc5a4e
Aug 10, 2023
- [RISCV] Stop performFP_TO_INTCombine from folding with ISD::FRINT. · 2df9328f
  Craig Topper authored Aug 10, 2023
  2df9328f
- [DAG] Support store merging of vector constant stores (try 2) · b1ada7a1
  Philip Reames authored Aug 10, 2023
  b1ada7a1
- Revert "[DAG] Support store merging of vector constant stores" · 0696a531
  Philip Reames authored Aug 10, 2023
  0696a531
- [RISCV] Remove completed FIXME. NFC · b165a777
  Luke Lau authored Aug 10, 2023
  b165a777
- [RISCV] Enable alias analysis by default · 5f73d2b7
  Yunze Zhu authored Aug 08, 2023
  5f73d2b7
Aug 08, 2023
- [RISCV] Lower vro{l,r} for fixed vectors · 5d510ea7
  Luke Lau authored Aug 07, 2023
  5d510ea7
- [RISCV] Lower unary zvbb ops for fixed vectors · 768740ef
  Luke Lau authored Aug 07, 2023
  768740ef
- [RISCV] Add fixed vector tests for ct[l,t]z_zero_undef · 44383ac7
  Luke Lau authored Aug 07, 2023
  44383ac7
- [RISCV] Use vmv.s.x for a constant build_vector when the entire size is less than 32 bits · f0a9aacd
  Philip Reames authored Aug 07, 2023
  f0a9aacd
Aug 07, 2023
- [RISCV] Use v(f)slide1down for build_vector with dominant values · 47fe3b3b
  Philip Reames authored Aug 07, 2023
  47fe3b3b
- [RISCVGatherScatterLowering] Support broadcast base pointer · 999ac10d
  Philip Reames authored Aug 07, 2023
  999ac10d
- [RISCV] Add a blank line after end of RUN lines. NFC. · f2bdc29f
  Jim Lin authored Aug 04, 2023
  f2bdc29f
Aug 04, 2023
- [RISCV] Add vector legalization for fmaximum/fminimum. · 81425019
  Craig Topper authored Aug 04, 2023
  81425019
Aug 03, 2023
- [RISCV] Add a test case that would have failed before D156974. NFC · 40f37082
  Craig Topper authored Aug 03, 2023
  40f37082
- [RISCV] Add tests that m extension enabled in extractelt-int-rv64.ll. NFC. · a2938ba7
  Jim Lin authored Aug 03, 2023
  a2938ba7
- [RISCV] Scalarize binop followed by extractelement to custom lowered instruction · 40cc106f
  Jim Lin authored Aug 03, 2023
  40cc106f
- [RISCV] Teach lowerScalarInsert to handle scalar value is the first element of a fixed vector. · cd795993
  Yeting Kuo authored Aug 02, 2023
  cd795993
- [RISCV] Add VP patterns for vwsll.[vv,vx,vi] · 08343552
  Luke Lau authored Aug 02, 2023
  08343552
Aug 02, 2023
- [DAG] Support store merging of vector constant stores · 660b740e
  Philip Reames authored Aug 02, 2023
  660b740e
- [RISCV] Support vector crypto extension LLVM IR · 346c1f26
  4vtomat authored Jun 25, 2023
  346c1f26