Commits · dd471bbb10ce94863819946e449804eb68ebd260 · Roger Ferrer / llvm-epi · GitLab

Jun 21, 2010
- Add missing FileCheck call. · dd471bbb
  Dale Johannesen authored Jun 21, 2010
  dd471bbb
- Fix PR 7433. Silly typo in non-Darwin ARM tail call · d5c58b76
  Dale Johannesen authored Jun 21, 2010
  d5c58b76
Jun 19, 2010
- Disable sibcall optimization for Thumb1 for now since... · f3c01f3e
  Evan Cheng authored Jun 19, 2010
  f3c01f3e
- Allow ARM if-converter to be run after post allocation scheduling. · 2d51c7c5
  Evan Cheng authored Jun 18, 2010
  2d51c7c5
- Fix an inverted condition. · cf9e8a98
  Evan Cheng authored Jun 18, 2010
  cf9e8a98
Jun 18, 2010
- When using ADDri to get the address of a stack object, 255 is a conservative · 22a212f9
  Jakob Stoklund Olesen authored Jun 18, 2010
  22a212f9
- Enable tail calls on ARM by default, with some · c1570dda
  Dale Johannesen authored Jun 18, 2010
  c1570dda
- Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 · b9f91667
  Jakob Stoklund Olesen authored Jun 18, 2010
  b9f91667
Jun 17, 2010
- Remove arm_apcscc from the test files. It is the default and doing this · 29dda21e
  Rafael Espindola authored Jun 17, 2010
  29dda21e
Jun 15, 2010
- Remove the local register allocator. · ec2e964f
  Jakob Stoklund Olesen authored Jun 15, 2010
  ec2e964f
- Set the mtriple in some tests so that they use AAPCS. · ae591be4
  Rafael Espindola authored Jun 15, 2010
  ae591be4
- Remove the arm_aapcscc marker from the tests. It is the default · 5a24a56e
  Rafael Espindola authored Jun 15, 2010
  5a24a56e
- Generalize the pre-coalescing of extract_subregs feeding reg_sequences, · a55b8877
  Bob Wilson authored Jun 15, 2010
  a55b8877
Jun 12, 2010
- Add a missing bitcast. This code used to only handle conversions between · f07d33d8
  Bob Wilson authored Jun 11, 2010
  f07d33d8
Jun 05, 2010
- Re-apply 105308 with fix. · a03e6f85
  Evan Cheng authored Jun 04, 2010
  a03e6f85
Jun 04, 2010
- More tail call removal. · 065d6fd5
  Dale Johannesen authored Jun 04, 2010
  065d6fd5
- Remove more tail calls. · b3780b11
  Dale Johannesen authored Jun 04, 2010
  b3780b11
- Remove a tail call, and move some CHECKs to the · e7b392dc
  Dale Johannesen authored Jun 04, 2010
  e7b392dc
Jun 03, 2010
- Revert 105308. · 30093b5d
  Bob Wilson authored Jun 03, 2010
  30093b5d
Jun 02, 2010
- Enable machine cse of instructions which define physical registers. · a2da2273
  Evan Cheng authored Jun 02, 2010
  a2da2273
May 29, 2010
- Fix some latency computation bugs: if the use is not a machine opcode do not just return zero. · cc2efe11
  Evan Cheng authored May 28, 2010
  cc2efe11
May 28, 2010
- Add a -regalloc=default option that chooses a register allocator based on the -O · b613ae2c
  Jakob Stoklund Olesen authored May 27, 2010
  b613ae2c
- llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error. · 3d3ee87d
  Evan Cheng authored May 27, 2010
  3d3ee87d
May 24, 2010
- LR is in GPR, not tGPR even in Thumb1 mode. · 755d45be
  Evan Cheng authored May 24, 2010
  755d45be
May 22, 2010
- Implement @llvm.returnaddress. rdar://8015977 . · 168ced94
  Evan Cheng authored May 22, 2010
  168ced94
- Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by · 91fdf685
  Bob Wilson authored May 22, 2010
  91fdf685
May 21, 2010
- Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements · 51d9ee3f
  Bob Wilson authored May 21, 2010
  51d9ee3f
- Teach VirtRegRewriter to handle spilling in instructions that have multiple · a648c6a7
  Jakob Stoklund Olesen authored May 21, 2010
  a648c6a7
- Change ARM scheduling default to list-hybrid if the target supports floating... · 34c26045
  Evan Cheng authored May 21, 2010
  34c26045
May 20, 2010
- When canonicalizing icmp operand order to put the loop invariant · ee2fea3c
  Dan Gohman authored May 20, 2010
  ee2fea3c
- Handle Neon v2f64 and v2i64 vector shuffles as register copies. · 5954994b
  Bob Wilson authored May 20, 2010
  5954994b
- Teach LSR how to cope better with unrolled loops on targets where · 20fab456
  Dan Gohman authored May 19, 2010
  20fab456
May 19, 2010
- TwoAddressInstructionPass doesn't really know how to merge live intervals when · e11cdf8c
  Jakob Stoklund Olesen authored May 19, 2010
  e11cdf8c
- Testcase to go with 104141. · f070b1b5
  Bob Wilson authored May 19, 2010
  f070b1b5
- Intrinsics which do a vector compare (results are all zero or all ones) are... · abd0ad54
  Evan Cheng authored May 19, 2010
  abd0ad54
- Remember to update VirtRegLastUse when spilling without killing before a call. · 430b6e40
  Jakob Stoklund Olesen authored May 18, 2010
  430b6e40
May 18, 2010
- Sink dag combine's post index load / store code that swap base ptr and index... · f19384d5
  Evan Cheng authored May 18, 2010
  f19384d5
- Fix PR7162: Use source register classes and sub-indices to determine the... · e7fc64a5
  Evan Cheng authored May 18, 2010
  e7fc64a5
- FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op... · 48f0de96
  Evan Cheng authored May 18, 2010
  48f0de96
- Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other... · 1e4f5520
  Evan Cheng authored May 17, 2010
  1e4f5520