Commits · dd48d3ad0e5fff78e6e3a7fd8ca830624ccb8e33 · Roger Ferrer / llvm-epi · GitLab

Nov 24, 2020
- Add support for branch forms of ALU instructions to Cortex-A57 model · 50bd6866
  Evgeny Leviant authored Nov 24, 2020
  50bd6866
Oct 26, 2020
- [ARM][SchedModels] Move IsLDMBaseRegInListPred to ARMSchedule.td. NFC · a28388f9
  Evgeny Leviant authored Oct 26, 2020
  a28388f9
- [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate · e74f6612
  Evgeny Leviant authored Oct 26, 2020
  e74f6612
- [ARM][SchedModels] Rename and generalize predicate. NFC · a95ce5f6
  Evgeny Leviant authored Oct 26, 2020
  
  a95ce5f6
- [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate · a4fc18e6
  Evgeny Leviant authored Oct 26, 2020
  a4fc18e6
- [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate · d613e39d
  Evgeny Leviant authored Oct 26, 2020
  d613e39d
Oct 23, 2020
- [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate · 7a78073b
  Evgeny Leviant authored Oct 23, 2020
  7a78073b
Oct 22, 2020
- [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate · ed6a91f4
  Evgeny Leviant authored Oct 22, 2020
  ed6a91f4
Oct 20, 2020
- [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate · 991e8615
  Evgeny Leviant authored Oct 20, 2020
  991e8615
Oct 19, 2020
- [ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate · 8a7ca143
  Evgeny Leviant authored Oct 19, 2020
  8a7ca143
Oct 14, 2020
- [ARM.td] Make instruction definitions visible to sched models · 2ad82b0e
  Evgeny Leviant authored Oct 14, 2020
  2ad82b0e
May 15, 2019
- [ARM] Cortex-M4 schedule · d2d0f46c
  David Green authored May 15, 2019
  d2d0f46c
Jan 19, 2019
- Update the file headers across all of the LLVM projects in the monorepo · 2946cd70
  Chandler Carruth authored Jan 19, 2019
  2946cd70
Aug 11, 2017
- [ARM] Assembler support for the ARMv8.2a dot product instructions · 7426c97b
  Sjoerd Meijer authored Aug 11, 2017
  7426c97b
Jun 28, 2017
- [ARM] Improve if-conversion for M-class CPUs without branch predictors · 75d76e5e
  John Brawn authored Jun 28, 2017
  75d76e5e
Jun 02, 2017
- [ARM] Cortex-A57 scheduling model for ARM backend (AArch32) · 4ae7e812
  Javed Absar authored Jun 02, 2017
  4ae7e812
May 24, 2017
- [ARM] Add VLDx/VSTx sched defs for machine-schedulers. NFCI · a32e3a1a
  Javed Absar authored May 24, 2017
  a32e3a1a
Feb 22, 2017
- [ARM] Classification Improvements to ARM Sched-Models. NFCI. · b6727228
  Javed Absar authored Feb 22, 2017
  b6727228
Feb 02, 2017
- [ARM] Classification Improvements to ARM Sched-Model. NFCI. · bb8dcc6a
  Javed Absar authored Feb 02, 2017
  bb8dcc6a
Jan 23, 2017
- [ARM] Classification Improvements to ARM Sched-Models. NFCI. · 00cce417
  Javed Absar authored Jan 23, 2017
  00cce417
Nov 15, 2016
- [ARM] Add machine scheduler for Cortex-R52 · f043dac2
  Javed Absar authored Nov 15, 2016
  f043dac2
Feb 23, 2016
- CodeGen: TII: Take MachineInstr& in predicate API, NFC · 6307eb55
  Duncan P. N. Exon Smith authored Feb 23, 2016
  6307eb55
Jan 25, 2016
- [ARM] Add ARMv8.2-A FP16 scalar instructions · 65b85382
  Oliver Stannard authored Jan 25, 2016
  65b85382
Dec 16, 2015
- Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions" · 187d33ee
  Reid Kleckner authored Dec 16, 2015
  187d33ee
- [ARM] Add ARMv8.2-A FP16 scalar instructions · 48568cbe
  Oliver Stannard authored Dec 16, 2015
  48568cbe
Jun 06, 2013
- ARM sched model: Add integer VFP/SIMD instructions on Swift · eac54473
  Arnold Schwaighofer authored Jun 06, 2013
  eac54473
Jun 05, 2013
- ARM sched model: Add divsion, loads, branches, vfp cvt · 2773f1de
  Arnold Schwaighofer authored Jun 05, 2013
  2773f1de
- Revert series of sched model patches until I figure out what is going on. · 2a70c69d
  Arnold Schwaighofer authored Jun 04, 2013
  2a70c69d
- ARM sched model: Add divsion, loads, branches, vfp cvt · d5b9794a
  Arnold Schwaighofer authored Jun 04, 2013
  d5b9794a
Apr 05, 2013
- ARM scheduler model: Add scheduler info to more instructions and resource · fb6b9f48
  Arnold Schwaighofer authored Apr 05, 2013
  fb6b9f48
- ARM scheduler model: Swift has varying latencies, uops for simple ALU ops · 5dde1f39
  Arnold Schwaighofer authored Apr 05, 2013
  5dde1f39
Apr 01, 2013
- ARM Scheduler Model: Add resources instructions, map resources in subtargets · 6793aebb
  Arnold Schwaighofer authored Apr 01, 2013
  6793aebb
Mar 26, 2013
- Revert ARM Scheduler Model: Add resources instructions, map resources · 414ef565
  Arnold Schwaighofer authored Mar 26, 2013
  414ef565
- ARM Scheduler Model: Add resources instructions, map resources in subtargets · ce639261
  Arnold Schwaighofer authored Mar 26, 2013
  ce639261
- ARM Scheduler Model: Partial implementation of the new machine scheduler model · fb1dddcc
  Arnold Schwaighofer authored Mar 26, 2013
  fb1dddcc
Sep 29, 2012
- Add LLVM support for Swift. · e8a549cd
  Bob Wilson authored Sep 29, 2012
  e8a549cd
Jul 02, 2012
- Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." · f161e391
  Andrew Trick authored Jul 02, 2012
  f161e391
Jun 29, 2012
- Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary." · 51a8cf77
  Andrew Trick authored Jun 29, 2012
  51a8cf77
- Make NumMicroOps a variable in the subtarget's instruction itinerary. · 1f50152b
  Andrew Trick authored Jun 29, 2012
  1f50152b
Jun 22, 2012
- Use "NoItineraries" for processors with no itineraries. · 9c302673
  Andrew Trick authored Jun 22, 2012
  9c302673