Commits · def26af4eab0e857edf24b5785b20652a61c5f88 · Roger Ferrer / llvm-epi · GitLab

Nov 09, 2020
- [llvm][AArch64] Allow TB(N)Z to drop signext for sign bit tests. · 9f61931e
  Francesco Petrogalli authored Nov 09, 2020
  9f61931e
- [FastISel] Reduce spills around mem-intrinsic calls · 920befb3
  Paul Robinson authored Nov 05, 2020
  920befb3
- [testing] Add exhaustive ULT/UGT vector CTPOP to AArch64 and PPC · d631e524
  David Zarzycki authored Nov 09, 2020
  d631e524
- [ARM][AArch64] Adding Neoverse V1 CPU support · c2c2cc13
  Lucas Prates authored Oct 28, 2020
  c2c2cc13
Nov 06, 2020
- [AArch64] Add pipeline model for HiSilicon's TSV110 · 93b99728
  Elvina Yakubova authored Nov 07, 2020
  93b99728
Nov 05, 2020
- [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. · f347d78c
  Amara Emerson authored Nov 04, 2020
  f347d78c
Nov 04, 2020
- [SelectionDAG] Add legalizations for VECREDUCE_SEQ_FMUL · c126eb75
  Cameron McInally authored Nov 04, 2020
  c126eb75
- [SVE][CodeGen] Lower scalable integer vector reductions · f2412d37
  Kerry McLaughlin authored Nov 04, 2020
  f2412d37
- [MachineInstr] Add support for instructions with multiple memory operands. · 4b112015
  Michael Liao authored Oct 12, 2020
  4b112015
- [AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD. · 393b5538
  Amara Emerson authored Nov 03, 2020
  393b5538
Nov 03, 2020
- Revert "[CodeGen] [WinException] Only produce handler data at the end of the function if needed" · cbf25fbe
  Hans Wennborg authored Nov 03, 2020
  cbf25fbe
- [AArch64][SVE] NFC: Guard all SVE tests for TypeSize warnings. · ba10c514
  Sander de Smalen authored Nov 03, 2020
  ba10c514
- [AArch64] Redundant masks in downcast long multiply · 54d86278
  Nicholas Guy authored Oct 22, 2020
  54d86278
Nov 02, 2020
- [Scheduling] Fall back to the fast cluster algorithm if the DAG is too complex · 1d178d60
  QingShan Zhang authored Nov 02, 2020
  1d178d60
Oct 30, 2020
- hwasan: Support for outlined checks in the Linux kernel. · 3d049bce
  Peter Collingbourne authored Oct 27, 2020
  3d049bce
- [Legalize] Add legalizations for VECREDUCE_SEQ_FADD · dda1e74b
  Cameron McInally authored Oct 30, 2020
  dda1e74b
- AArch64: Use SBFX instead of UBFX to extract address granule in outlined HWASan checks. · c9b1a2b4
  Peter Collingbourne authored Oct 27, 2020
  c9b1a2b4
- AArch64: Switch to x20 as the shadow base register for outlined HWASan checks. · 3859fc65
  Peter Collingbourne authored Oct 27, 2020
  3859fc65
- [SVE] Add fatal error for unnamed SVE variadic arguments · cea69fa4
  David Sherwood authored Oct 27, 2020
  cea69fa4
Oct 29, 2020
- [SDAG] Fix neutral value for vecreduce_fadd · a5f17292
  Nikita Popov authored Oct 29, 2020
  a5f17292
- [CodeGen] Fix neutral value of vecreduce fadd in tests (NFC) · fa48ff3f
  Nikita Popov authored Oct 29, 2020
  fa48ff3f
- [InterleaveAccess] Recognise Interleave loads through binary operations · a4b6b1e1
  David Green authored Oct 29, 2020
  a4b6b1e1
Oct 28, 2020
- [AArch64] Improve lowering of insert_vector_elt with 0.0 consts. · 772aaa60
  Florian Hahn authored Oct 28, 2020
  772aaa60
- [AArch64] Use DUP for BUILD_VECTOR with few different elements. · ba78cae2
  Florian Hahn authored Oct 28, 2020
  ba78cae2
- [GISel]: Few InsertVecElt combines · bed83940
  Aditya Nandakumar authored Oct 28, 2020
  bed83940
- [AArch64] Extend vector insertion test cases. · 5febc535
  Florian Hahn authored Oct 28, 2020
  5febc535
- [AArch64] Remove AArch64ISD::NOT, use vnot instead · 066737fd
  David Green authored Oct 28, 2020
  066737fd
Oct 27, 2020
- [AArch64] Add additional tests for vector inserts with common element. · 548772fe
  Florian Hahn authored Oct 27, 2020
  
  548772fe
- [ARM][AArch64] Add VLDN shuffled interleaving tests. NFC · ad299364
  David Green authored Oct 27, 2020
  
  ad299364
Oct 26, 2020
- [AArch64] Extend tests for insertelement improvements. · 89485efc
  Florian Hahn authored Oct 26, 2020
  89485efc
- [SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination · 5b742a0c
  Peter Waller authored Oct 19, 2020
  5b742a0c
- Revert "[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination" · 6536d604
  Peter Waller authored Oct 26, 2020
  6536d604
- [SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination · 46044413
  Peter Waller authored Oct 19, 2020
  46044413
- [AArch64] Add 2 cases where insertelement lowering could be improved. · a562dc82
  Florian Hahn authored Oct 26, 2020
  
  a562dc82
- Try to fix buildbots after d3205bbc · 4afa0778
  Tyker authored Oct 26, 2020
  
  4afa0778
- [AsmPrinter] Add per BB instruction mix remark. · b2bec7ce
  Florian Hahn authored Oct 26, 2020
  b2bec7ce
Oct 24, 2020
- [LegalizeTypes] Legalize vector rotate operations · 62b17a76
  Simon Pilgrim authored Oct 24, 2020
  62b17a76
Oct 23, 2020
- [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation · a1cc274c
  Cameron McInally authored Oct 23, 2020
  a1cc274c
- [AArch64][GlobalISel] Introduce a new post-isel optimization pass. · 0f0fd383
  Amara Emerson authored Oct 13, 2020
  0f0fd383
- [AArch64][SVE] Fix umin/umax lowering to handle out of range imm. · 1e113c07
  Huihui Zhang authored Oct 23, 2020
  1e113c07