Commits · defe11866a326491ee9767f84bb3f70cfc4f4bcb · Roger Ferrer / llvm-epi · GitLab

Nov 05, 2020
- [RISCV] Add isel patterns for fnmadd/fnmsub with an fneg on the second operand... · defe1186
  Craig Topper authored Nov 05, 2020
  defe1186
- [RISCV] Add test cases to show missed opportunities to use fnmadd/fnmsub if... · 4a4f4f78
  Craig Topper authored Nov 05, 2020
  4a4f4f78
- [VE] Add isReMaterializable and isAsCheapAsAMove flags · f0e585d5
  Kazushi (Jam) Marukawa authored Nov 03, 2020
  f0e585d5
- [MachineOutliner] Do not outline debug instructions · 5b30d9ad
  Momchil Velikov authored Nov 05, 2020
  5b30d9ad
- [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. · f347d78c
  Amara Emerson authored Nov 04, 2020
  f347d78c
- [RISCV] Use the 'si' lib call for (double (fp_to_sint/uint i32 X)) when F extension is enabled. · ce5f4f22
  Craig Topper authored Nov 05, 2020
  ce5f4f22
- [AMDGPU] Add default 1 glc operand to rtn atomics · f738aee0
  Stanislav Mekhanoshin authored Nov 03, 2020
  f738aee0
- [RISCV] Add isel patterns for fshl with immediate to select FSRI/FSRIW · c623584b
  Craig Topper authored Nov 05, 2020
  c623584b
- [GlobalISel] ComputeKnownBits - use common KnownBits shift handling (PR44526) · 546d002d
  Simon Pilgrim authored Nov 05, 2020
  546d002d
- [ARM] Make tests less dependent on scheduling. NFC · f38d1a95
  David Green authored Nov 05, 2020
  
  f38d1a95
- [NewPM] Provide method to run all pipeline callbacks, used for -O0 · ae385400
  Arthur Eubanks authored Oct 30, 2020
  ae385400
- [MachineSink] add more profitable pattern. · f645cea8
  Chen Zheng authored Sep 21, 2020
  f645cea8
- Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new... · 574de837
  Craig Topper authored Nov 04, 2020
  574de837
- Revert "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new... · 7709d306
  Craig Topper authored Nov 04, 2020
  7709d306
- [RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC · 36072cc0
  Craig Topper authored Nov 04, 2020
  36072cc0
- [X86] Enable shrink-wrapping for no-frame-pointer non-nounwind functions on... · 96b0b9a5
  Fangrui Song authored Nov 04, 2020
  96b0b9a5
Nov 04, 2020
- [SelectionDAG] Add legalizations for VECREDUCE_SEQ_FMUL · c126eb75
  Cameron McInally authored Nov 04, 2020
  c126eb75
- [RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions. · d47300f5
  Craig Topper authored Nov 04, 2020
  d47300f5
- [DAGCombine] Fix bug in load scalarization · f99580c1
  Fraser Cormack authored Apr 21, 2020
  f99580c1
- [RISCV] Check all 64-bits of the mask in SelectRORIW. · 857563ea
  Craig Topper authored Nov 04, 2020
  857563ea
- [AMDGPU] Resolve pseudo registers at encoding uses · 58adab34
  Joe Nash authored Nov 03, 2020
  58adab34
- [AMDGPU] Fix iterating in SIFixSGPRCopies · 31a0b283
  Sebastian Neubauer authored Oct 29, 2020
  31a0b283
- [VE] Add +vpu attribute · 351c10cc
  Simon Moll authored Nov 04, 2020
  351c10cc
- [SVE][CodeGen] Lower scalable integer vector reductions · f2412d37
  Kerry McLaughlin authored Nov 04, 2020
  f2412d37
- [AMDGPU] Set rsrc1 flags for graphics shaders · 1124bf4a
  Sebastian Neubauer authored Oct 14, 2020
  1124bf4a
- [AMDGPU] Fix ieee mode default value · 76313288
  Sebastian Neubauer authored Oct 14, 2020
  76313288
- [RISCV] Add fshl with immediate tests for Zbt extension. NFC · d3415232
  Craig Topper authored Nov 03, 2020
  d3415232
- [StackColoring] Conservatively merge catch point of V for catch(V) · 7ba32936
  Xiang1 Zhang authored Nov 03, 2020
  7ba32936
- [MachineInstr] Add support for instructions with multiple memory operands. · 4b112015
  Michael Liao authored Oct 12, 2020
  4b112015
- [AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD. · 393b5538
  Amara Emerson authored Nov 03, 2020
  393b5538
Nov 03, 2020
- [WebAssembly] Don't fold frame offset for global addresses · 0fca6517
  Julien Jorge authored Nov 01, 2020
  0fca6517
- [ARM] remove cost-kind predicate for most math op costs · c40126e7
  Sanjay Patel authored Nov 03, 2020
  c40126e7
- [RISCV] Add missing patterns for rotr with immediate for Zbb/Zbp extensions. · 00eff96e
  Craig Topper authored Nov 03, 2020
  00eff96e
- [DAG] computeKnownBits - Move (most) ISD::SRL handling into KnownBits::lshr · cb798f04
  Simon Pilgrim authored Nov 03, 2020
  cb798f04
- [AMDGPU] Regenerate load i16 tests to use update_llc_test_checks.py script. NFCI. · c06c02bd
  Simon Pilgrim authored Nov 03, 2020
  c06c02bd
- Revert "[PowerPC] Extend folding RLWINM + RLWINM to post-RA." · 5053eab8
  Esme-Yi authored Nov 03, 2020
  5053eab8
- [AMDGPU] Add gfx1033 target · 89d41f3a
  Tim Renouf authored Oct 30, 2020
  89d41f3a
- [AMDGPU] Add gfx90c target · ee3e6426
  Tim Renouf authored Oct 06, 2020
  ee3e6426
- [AMDGPU] Fix ds_read2/write2 with unaligned offsets · 040c5027
  Jay Foad authored Nov 02, 2020
  040c5027
- [AMDGPU] Precommit globalisel tests for ds_read2_b64 with large offset · 6e008cb5
  Jay Foad authored Nov 03, 2020
  
  6e008cb5