Commits · df19e57a1c39feb0c89170ffdb3a335f78d4bccf · Roger Ferrer / llvm-epi · GitLab

Nov 01, 2018
- [COFF, ARM64] Implement llvm.addressofreturnaddress intrinsic · df19e57a
  Mandeep Singh Grang authored Nov 01, 2018
  df19e57a
- [WebAssembly] Fixup `main` signature by default · ddf04986
  Sam Clegg authored Nov 01, 2018
  ddf04986
- [GlobalISel] Fix a bug in LegalizeRuleSet::clampMaxNumElements · 0a8dc9eb
  Volkan Keles authored Nov 01, 2018
  0a8dc9eb
- Revert "[COFF, ARM64] Implement Intrinsic.sponentry for AArch64" · b0cdf56d
  Mandeep Singh Grang authored Nov 01, 2018
  b0cdf56d
- [DAGCombiner] make sure we have a whole-number extract before trying to narrow... · c5fe3ce2
  Sanjay Patel authored Nov 01, 2018
  c5fe3ce2
- [MC] Implement EmitRawText in MCNullStreamer · 29ca7644
  Daniel Sanders authored Nov 01, 2018
  29ca7644
- [ARM][CGP] Negative constant operand handling · 84a2f8b3
  Sam Parker authored Nov 01, 2018
  84a2f8b3
- [mips][micromips] Fix JmpLink to TargetExternalSymbol · b9c840c9
  Aleksandar Beserminji authored Nov 01, 2018
  b9c840c9
- [X86][SSE] Move 2-input limit up from getFauxShuffleMask to resolveTargetShuffleInputs (reapplied) · 1f0a8421
  Simon Pilgrim authored Nov 01, 2018
  1f0a8421
- [Mips] Conditionally remove successor block · cd0c50e3
  Stefan Maksimovic authored Nov 01, 2018
  cd0c50e3
- [PowerPC] Support constraint 'wi' in asm · 03170a90
  Li Jia He authored Nov 01, 2018
  03170a90
- [WebAssembly] Lower vselect · d4891a1b
  Thomas Lively authored Nov 01, 2018
  d4891a1b
- [WebAssembly] Process p2align operands for SIMD loads and stores · b61232ea
  Thomas Lively authored Oct 31, 2018
  b61232ea
- [WebAssembly] Handle vector IMPLICIT_DEFs. · 6ff31fe3
  Thomas Lively authored Oct 31, 2018
  6ff31fe3
- [COFF, ARM64] Implement Intrinsic.sponentry for AArch64 · 88ad9ac7
  Mandeep Singh Grang authored Oct 31, 2018
  88ad9ac7
- [IR] Allow increasing the alignment of dso-local globals. · d548f0a2
  Eli Friedman authored Oct 31, 2018
  d548f0a2
Oct 31, 2018
- Revert r345165 "[X86] Bring back the MOV64r0 pseudo instruction" · 6c3f1692
  Craig Topper authored Oct 31, 2018
  6c3f1692
- [ARM] Add missing pseudo-instruction for Thumb1 RSBS. · 063fd98b
  Eli Friedman authored Oct 31, 2018
  063fd98b
- Check shouldReduceLoadWidth from SimplifySetCC · 222e9c11
  Stanislav Mekhanoshin authored Oct 31, 2018
  222e9c11
- [SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt · 92bb783c
  Scott Linder authored Oct 31, 2018
  92bb783c
- [AMDGPU] Remove FeatureVGPRSpilling · c6c62725
  Scott Linder authored Oct 31, 2018
  c6c62725
- [globalisel][irtranslator] Fix test from r345743 on non-asserts builds. · a01348fa
  Daniel Sanders authored Oct 31, 2018
  a01348fa
- [globalisel][irtranslator] Verify that DILocations aren't lost in translation · 3b39040a
  Daniel Sanders authored Oct 31, 2018
  3b39040a
- MachineModuleInfo: Initialize DbgInfoAvailable depending on debug_cus existing · 8763c0c5
  Matthias Braun authored Oct 31, 2018
  8763c0c5
- [Hexagon] Make sure not to use GP-relative addressing with PIC · 977a1fe5
  Krzysztof Parzyszek authored Oct 31, 2018
  977a1fe5
- [DAGCombiner] Fold 0 div/rem X to 0 · d0080c3a
  David Bolvansky authored Oct 31, 2018
  d0080c3a
- AMDGPU: Rewrite SILowerI1Copies to always stay on SALU · 814abb59
  Nicolai Haehnle authored Oct 31, 2018
  814abb59
- AMDGPU: Remove PHI loop condition optimization · 28212cc6
  Nicolai Haehnle authored Oct 31, 2018
  28212cc6
- [AMDGPU] support image load/store a16 · 63718b21
  Neil Henning authored Oct 31, 2018
  63718b21
- [ARM64] [Windows] Exception handling support in frame lowering · fadebc8a
  Sanjin Sijaric authored Oct 31, 2018
  fadebc8a
- [AArch64] Mark condition flags and x16/x17 as clobbered when calling __chkstk · 315357fa
  Martin Storsjö authored Oct 31, 2018
  315357fa
- MachineOperand/MIParser: Do not print debug-use flag, infer it · a8340389
  Matthias Braun authored Oct 30, 2018
  a8340389
Oct 30, 2018
- [ARM][NFC] Make tests immune to better div optimizations · f739066e
  David Bolvansky authored Oct 30, 2018
  f739066e
- Revert r345542: AMDGPU: Enable code object v3 by default · 2d22d24a
  Konstantin Zhuravlyov authored Oct 30, 2018
  2d22d24a
- [FPEnv] [FPEnv] Add constrained intrinsics for MAXNUM and MINNUM · 2ad870e7
  Cameron McInally authored Oct 30, 2018
  2ad870e7
- [x86] try to make test immune to better div optimization; NFCI · caf5f5c4
  Sanjay Patel authored Oct 30, 2018
  caf5f5c4
- [COFF, ARM64] Make sure to forward arguments from vararg to musttail vararg · 71e0cc2a
  Mandeep Singh Grang authored Oct 30, 2018
  71e0cc2a
- [x86] try to make test immune to better div optimization; NFCI · 00935bc1
  Sanjay Patel authored Oct 30, 2018
  00935bc1
- [x86] try to make test immune to better div optimization; NFCI · 059ebc90
  Sanjay Patel authored Oct 30, 2018
  059ebc90
- [DAGCombiner] Fix for big endian in ForwardStoreValueToDirectLoad · fe09a20f
  Bjorn Pettersson authored Oct 30, 2018
  fe09a20f