Commits · df323ba445f7fc4d29def8950e80dec6ba487961 · Roger Ferrer / llvm-epi · GitLab

Apr 29, 2021
- Revert "[X86] Support AMX fast register allocation" · df323ba4
  Benjamin Kramer authored Apr 29, 2021
  df323ba4
- [RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) ->... · dcdda2bd
  Craig Topper authored Apr 29, 2021
  dcdda2bd
- [COST] Improve shuffle kind detection if shuffle mask is provided. · 92399322
  Alexey Bataev authored Apr 20, 2021
  92399322
- [AsmParser][SystemZ][z/OS] Reject "Dot" as current PC on z/OS · ded0a70a
  Anirudh Prasad authored Apr 29, 2021
  ded0a70a
- [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32. · 0c330afd
  Craig Topper authored Apr 29, 2021
  0c330afd
- [RISCV] Teach computeKnownBits that vsetvli returns number less than 2^31. · 25391cec
  Craig Topper authored Apr 29, 2021
  25391cec
- [AArch64][SVE] Use SIMD variant of INSR when scalar is the result of a vector extract · 354604a2
  Bradley Smith authored Apr 23, 2021
  354604a2
- [AArch64][SVE] Convert svdup(vec, SV_VL1, elm) to insertelement(vec, elm, 0) · 89085bcc
  Bradley Smith authored Apr 23, 2021
  89085bcc
- [AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine · c8f20ed4
  Bradley Smith authored Apr 26, 2021
  c8f20ed4
- [AMDGPU] Allow buildSpillLoadStore in empty bb · 9569d5ba
  Sebastian Neubauer authored Apr 29, 2021
  9569d5ba
- [ARM] Ensure CSINC has one use in CSINV combine · e11420ca
  David Green authored Apr 29, 2021
  e11420ca
- [NVPTX] Fix unused var warning with asserts disabled · 54ee962e
  David Spickett authored Apr 29, 2021
  54ee962e
- [SPE] Support constrained float operations on SPE · 56d923ef
  Qiu Chaofan authored Apr 29, 2021
  56d923ef
- [RISCV] Fix stack slot for argument types (Bug 49500) · 43ad058a
  Fraser Cormack authored Mar 22, 2021
  43ad058a
- [X32][CET] Fix handling of indirect branches · 1b788607
  Harald van Dijk authored Apr 29, 2021
  1b788607
- [ARM] Use just ARM::t2B in ARMBlockPlacementPass · 465df353
  David Green authored Apr 29, 2021
  465df353
Apr 28, 2021
- [AArch64][GlobalISel] Don't match thread-local globals in matchFoldGlobalOffset · 4d41810c
  Jessica Paquette authored Apr 28, 2021
  4d41810c
- [AsmParser][SystemZ][z/OS] Use updated framework in AsmLexer to accept special... · 07b0a72d
  Anirudh Prasad authored Apr 28, 2021
  07b0a72d
- [AMDGPU] Make some VOP3 insts commutable · 168228d7
  Joe Nash authored Mar 29, 2021
  168228d7
- [RISCV] Add explanatory comment to RISCVOp::OPERAND_AVL. · 1d4d6a96
  Craig Topper authored Apr 28, 2021
  
  1d4d6a96
- [ARM][AArch64] Require appropriate features for crypto algorithms · b8baa2a9
  David Candler authored Apr 28, 2021
  b8baa2a9
- [Hexagon] Skip function in Hexagon vector combine if requested · 899352c7
  Krzysztof Parzyszek authored Apr 28, 2021
  899352c7
- [PowerPC] Fix SELECT_CC with i64 operand on PPC32 · d5c24924
  Qiu Chaofan authored Apr 28, 2021
  d5c24924
- [AArch64] Add missing UINT_TO_FP promotions for v16i8 · 1eb81f83
  Joe Ellis authored Apr 26, 2021
  1eb81f83
- [X86][AMX][NFC] Add more comments and remove unnecessary check found by Clocwork · f69adfb8
  Wang, Pengfei authored Apr 28, 2021
  
  f69adfb8
- [NFC] Refactor how CFI section types are represented in AsmPrinter · 63cfab4f
  RamNalamothu authored Apr 28, 2021
  63cfab4f
- [WebAssembly] Error when wasm EH is used with Emscripten EH/SjLj · b4a5dd4d
  Heejin Ahn authored Apr 27, 2021
  b4a5dd4d
Apr 27, 2021
- [SelectionDAG] Use a VTSDNode to store the saturation width for FP_TO_SINT_SAT/FP_TO_UINT_SAT · 3067520b
  Craig Topper authored Apr 27, 2021
  3067520b
- [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing... · ce09dd54
  Craig Topper authored Apr 27, 2021
  ce09dd54
- [AMDGPU] GCNHazardRecognizer: ignore all meta instructions · 12011b52
  Jay Foad authored Apr 27, 2021
  12011b52
- [ARM] Recognize VIDUP from BUILDVECTORs of additions · 8de7d8b2
  David Green authored Apr 27, 2021
  8de7d8b2
- [COST][X86]Improve cost model for reverse shuffle v32i16/v64i8 in AVX512F. · f19e8f42
  Alexey Bataev authored Apr 21, 2021
  f19e8f42
- [SystemZ][z/OS] Remove register prefixes when printing out the register. · 21db4cc2
  Anirudh Prasad authored Apr 27, 2021
  21db4cc2
- [CodeGenOptions] make StackProtectorGuardOffset signed · ea8416bf
  Nick Desaulniers authored Apr 27, 2021
  ea8416bf
- [AIX][Power10] Restrict prefixed instructions from crossing the 64byte boundary · 241c2da4
  Victor Huang authored Apr 22, 2021
  241c2da4
- Revert rG9b7a0a50355d5 - Revert "[X86] Add support for reusing ZF etc. from... · decab8e9
  Simon Pilgrim authored Apr 27, 2021
  decab8e9
- [X86] Add support for reusing ZF etc. from locked XADD instructions (PR20841) · 9b7a0a50
  Simon Pilgrim authored Apr 27, 2021
  9b7a0a50
- [AMDGPU] Minor refactoring in AMDGPUUnifyDivergentExitNodes. NFC. · dc2f6bf5
  Jay Foad authored Apr 27, 2021
  dc2f6bf5
- [X86] Ensure multiclass ATOMIC_RMW_BINOP is tagged as MayLoad and MayStore · 029e41ec
  Simon Pilgrim authored Apr 27, 2021
  029e41ec
- AMDGPU/GlobalISel: Fix negative offset folding for buffer_load · 8110fcc8
  Petar Avramovic authored Apr 27, 2021
  8110fcc8