Commits · df773ebb5f8ff54cda385f4491ff877464228c18 · Roger Ferrer / llvm-epi · GitLab

Nov 26, 2019
- [AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier. · 008e65a7
  vpykhtin authored Nov 18, 2019
  008e65a7
- Revert "As a follow-up to my initial mail to llvm-dev here's a first pass at... · c9ddb026
  Muhammad Omair Javaid authored Nov 26, 2019
  c9ddb026
- As a follow-up to my initial mail to llvm-dev here's a first pass at the O1 described there. · 8ff85ed9
  Eric Christopher authored Nov 25, 2019
  8ff85ed9
Nov 23, 2019
- AMDGPU: Handle waitcnt overflow · fef69706
  Austin Kerbow authored Nov 02, 2019
  fef69706
Nov 21, 2019
- [AMDGPU] Add attribute for target loop unroll threshold default · 6821a3cc
  Tim Corringham authored Oct 11, 2019
  6821a3cc
Nov 20, 2019
- [AMDGPU][SILoadStoreOptimizer] Merge TBUFFER loads/stores · 4a801170
  Piotr Sobczak authored Nov 20, 2019
  4a801170
- [AMDGPU] Fixed mfma test check. NFC. · 899cdf95
  Stanislav Mekhanoshin authored Nov 20, 2019
  
  899cdf95
- [AMDGPU] Keep consistent check of legal addressing mode. · 4a308d30
  Michael Liao authored Nov 19, 2019
  4a308d30
- [AMDGPU] add support for hostcall buffer pointer as hidden kernel argument · 52c5014d
  Sameer Sahasrabuddhe authored Nov 19, 2019
  52c5014d
- AMDGPU/GlobalISel: Legalize FDIV64 · f3225f2a
  Austin Kerbow authored Nov 17, 2019
  f3225f2a
Nov 19, 2019
- AMDGPU: Refactor treatment of denormal mode · db0ed3e4
  Matt Arsenault authored Oct 31, 2019
  db0ed3e4
- AMDGPU: Be explicit about denormal mode in MIR tests · ea23b642
  Matt Arsenault authored Nov 01, 2019
  ea23b642
- [AMDGPU] Tune inlining parameters for AMDGPU target (part 2) · 6fd11b14
  dfukalov authored Nov 18, 2019
  6fd11b14
Nov 15, 2019
- [AMDGPU] Lower llvm.amdgcn.s.buffer.load.v3[i|f]32 · 02419ab5
  Piotr Sobczak authored Nov 12, 2019
  02419ab5
- AMDGPU: Change boolean content type to 0 or 1 · 31479d86
  Matt Arsenault authored Nov 11, 2019
  31479d86
- AMDGPU: Try to commute sub of boolean ext · 69fcfb7d
  Matt Arsenault authored Nov 14, 2019
  69fcfb7d
- GlobalISel: Lower s1 source G_SITOFP/G_UITOFP · bc276c63
  Matt Arsenault authored Nov 15, 2019
  
  bc276c63
Nov 14, 2019
- [AMDGPU] Fixed dpp test. NFC. · 4fa44f98
  Stanislav Mekhanoshin authored Nov 13, 2019
  
  4fa44f98
- [AMDGPU] Fixed mfma-loop test. NFC. · af7d4022
  Stanislav Mekhanoshin authored Nov 13, 2019
  
  af7d4022
Nov 13, 2019
- AMDGPU: Extend add x, (ext setcc) combine to sub · 9d7bccab
  Matt Arsenault authored Nov 12, 2019
  9d7bccab
- AMDGPU: Switch backend default max workgroup size to 1024 · 4b472139
  Matt Arsenault authored Aug 27, 2019
  4b472139
- AMDGPU Reduce reported maximum group size to 1024 · 25c5da5a
  Matt Arsenault authored Aug 27, 2019
  25c5da5a
Nov 12, 2019
- MCP: Fixed bug with dest overlapping copy source · 07ebd741
  Tim Renouf authored Nov 11, 2019
  07ebd741
Nov 07, 2019
- AMDGPU: Select global atomicrmw fadd · e16a7138
  Matt Arsenault authored Aug 29, 2019
  e16a7138
- [AMDGPU] Add handling of 160 bit registers in analyzeResourceUsage · d17bcf2b
  Stanislav Mekhanoshin authored Nov 06, 2019
  d17bcf2b
Nov 06, 2019
- [GISel][ArtifactCombiner] Relax the constraint to combine unmerge with concat_vectors · 52af7aed
  Quentin Colombet authored Nov 06, 2019
  52af7aed
Nov 05, 2019
- [globalisel] Rename G_GEP to G_PTR_ADD · e74c5b96
  Daniel Sanders authored Nov 01, 2019
  e74c5b96
Nov 01, 2019
- [amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`. · 4531aee2
  Michael Liao authored Nov 01, 2019
  4531aee2
Oct 30, 2019
- AMDGPU: Disallow spill folding with m0 copies · d9e0a294
  Matt Arsenault authored Oct 30, 2019
  d9e0a294
- AMDGPU: Don't fold S_NOPs with implicit operands · edca9ac0
  Matt Arsenault authored Oct 30, 2019
  
  edca9ac0
- [AMDGPU] Simplify VCCZ bug handling · e5972f2a
  Jay Foad authored Oct 30, 2019
  e5972f2a
- [SelectionDAG] Add support for FP_ROUND in WidenVectorOperand. · 86549c75
  Jay Foad authored Oct 23, 2019
  86549c75
- AMDGPU/GlobalISel: Legalize FDIV32 · 2b88b344
  Austin Kerbow authored Oct 29, 2019
  2b88b344
Oct 29, 2019
- AMDGPU: Make VReg_1 only include 1 artificial register · 21bc8e5a
  Matt Arsenault authored Oct 28, 2019
  21bc8e5a
Oct 28, 2019
- AMDGPU: Avoid overwriting saved PC · d11b93ec
  Austin Kerbow authored Oct 28, 2019
  d11b93ec
Oct 26, 2019
- [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. · e921ede5
  cdevadas authored Oct 26, 2019
  e921ede5
- [SDAG] fold extract_vector_elt with undef index · 4c476176
  Sanjay Patel authored Oct 25, 2019
  4c476176
- [AMDGPU] Enable SGPR copy folding · 4c0251da
  Stanislav Mekhanoshin authored Oct 25, 2019
  4c0251da
Oct 25, 2019
- GlobalISel: Implement widenScalar for G_INSERT_VECTOR_ELT · 1a276d1e
  Matt Arsenault authored Oct 01, 2019
  
  1a276d1e
- AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG · 171cf530
  Matt Arsenault authored Oct 08, 2019
  171cf530