Commits · e087b4f14986f8330336b005c6ebb41f2bdaea63 · Roger Ferrer / llvm-epi · GitLab

Jun 12, 2021
- Revert "[X86FixupLEAs] Sub register usage of LEA dest should block LEA/SUB optimization" · e087b4f1
  Florian Hahn authored Jun 12, 2021
  e087b4f1
- [AMDGPU][IndirectCalls] Fix register usage propagation for indirect/external calls · c27e8141
  madhur13490 authored Jun 03, 2021
  c27e8141
Jun 11, 2021
- AMDGPU/GlobalISel: Remove leftover hack for argument memory sizes · a845dc1e
  Matt Arsenault authored Jun 10, 2021
  a845dc1e
- AMDGPU/GlobalISel: Fix indentation · 6dd54dad
  Matt Arsenault authored Jun 10, 2021
  
  6dd54dad
- [X86FixupLEAs] Sub register usage of LEA dest should block LEA/SUB optimization · f35bcea1
  Guozhi Wei authored Jun 11, 2021
  f35bcea1
- [ADT] Remove APInt/APSInt toString() std::string variants · 61cdaf66
  Simon Pilgrim authored Jun 11, 2021
  61cdaf66
- [PowerPC] Allow wa inline asm to also accept floating point arguments · c1bb75fe
  Zarko Todorovski authored Jun 10, 2021
  c1bb75fe
- Do not generate calls to the 128-bit function __multi3() on 32-bit ARM · 78970861
  Koutheir Attouchi authored Jun 11, 2021
  78970861
- [CostModel][AArch64] Improve the cost estimate of CTPOP intrinsic · d7c219a5
  Rosie Sumpter authored Jun 09, 2021
  d7c219a5
- [X86] Support __tile_stream_loadd intrinsic for new AMX interface · 56d5c46b
  Bing1 Yu authored Jun 11, 2021
  56d5c46b
- [Analysis] Pass RecurrenceDescriptor as const reference. NFCI. · 5e6bfb66
  Simon Pilgrim authored Jun 11, 2021
  5e6bfb66
- [PowerPC] Relax register superclasses for paired memops · bc104fdc
  Qiu Chaofan authored Jun 11, 2021
  bc104fdc
- [RISCV] Avoid scalar outgoing argumetns overwriting vector frame objects. · 643b6407
  Hsiangkai Wang authored Jun 03, 2021
  643b6407
- [RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32. · 420bd5ee
  Craig Topper authored Jun 10, 2021
  420bd5ee
- [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes. · 670edf3e
  Amara Emerson authored Jun 10, 2021
  670edf3e
- [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF · 933df6ca
  Jessica Paquette authored Jun 10, 2021
  933df6ca
Jun 10, 2021
- [ARM] Fix Changed status in MVEGatherScatterLoweringPass. · 5d5b686f
  David Green authored Jun 10, 2021
  5d5b686f
- [ARM] Ensure instructions are simplified prior to GatherScatter lowering. · e0c605f6
  David Green authored Jun 10, 2021
  e0c605f6
- [AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them · 1b894ccd
  Jessica Paquette authored Jun 09, 2021
  1b894ccd
- [AArch64] Silence fallthrough warning. NFC. · 3dceffd0
  Benjamin Kramer authored Jun 10, 2021
  3dceffd0
- [X86][NFC] Fix typo. · 63233da7
  Luo, Yuanke authored Jun 10, 2021
  
  63233da7
- [AArch64] Add cost tests for bitreverse · de79919e
  Irina Dobrescu authored Jun 03, 2021
  de79919e
- [ARM] Skip debug during vpt block creation · 9872551c
  David Green authored Jun 10, 2021
  9872551c
- [llvm][PPC] Add missing case for 'I' asm memory operands · a9e4f91a
  Timm Bäder authored Jun 10, 2021
  a9e4f91a
- Revert "Implementation of global.get/set for reftypes in LLVM IR" · 64de8763
  David Spickett authored Jun 10, 2021
  64de8763
- [TargetLowering] getABIAlignmentForCallingConv - pass DataLayout by const reference. NFCI. · 4eb47e3c
  Simon Pilgrim authored Jun 09, 2021
  4eb47e3c
- Implementation of global.get/set for reftypes in LLVM IR · 31859f89
  Paulo Matos authored Jun 10, 2021
  31859f89
- Revert "[AArch64LoadStoreOptimizer] Generate more STPs by renaming registers earlier" · 99653702
  Martin Storsjö authored Jun 10, 2021
  99653702
- [AMDGPU] Fix missing lowering of LDS used in global scope. · f6632f11
  hsmahesha authored Jun 10, 2021
  f6632f11
- [AIX] Add traceback ssp canary bit support · 4a89ed37
  Jinsong Ji authored Jun 10, 2021
  4a89ed37
- [RISCV] Remove unused method from RISCVInsertVSETVLI. NFC · 8dfd0810
  Craig Topper authored Jun 09, 2021
  8dfd0810
Jun 09, 2021
- Revert "Do not generate calls to the 128-bit function __multi3() on 32-bit ARM" · 68a1d9a1
  Nico Weber authored Jun 09, 2021
  68a1d9a1
- Do not generate calls to the 128-bit function __multi3() on 32-bit ARM · 64e9aa33
  Koutheir Attouchi authored Jun 09, 2021
  64e9aa33
- [X86] Check destination element type before forming VTRUNCS/VTRUNCUS in combineTruncateWithSat. · 765ef4bb
  Craig Topper authored Jun 09, 2021
  765ef4bb
- [ARM] Fix Machine Outliner LDRD/STRD handling in Thumb mode. · 6c78dbd4
  Yvan Roux authored Jun 09, 2021
  6c78dbd4
- [X86][SLM] Adjust XMM non-PMULLD throughput costs to half rate. · 630820ba
  Simon Pilgrim authored Jun 09, 2021
  630820ba
- [AArch64LoadStoreOptimizer] Generate more STPs by renaming registers earlier · d96ea466
  Meera Nakrani authored Jun 02, 2021
  d96ea466
- [ValueTypes][RISCV] Cap RVV fixed-length vectors by size · 502edebd
  Fraser Cormack authored Jun 07, 2021
  502edebd
- [RISCV] Support CONCAT_VECTORS on scalable masks · e8f1f891
  Fraser Cormack authored Jun 08, 2021
  e8f1f891
- [PowerPC] Make sure the first probe is full size or is the last probe when stack is realigned · bf58600b
  Kai Luo authored Jun 09, 2021
  bf58600b