Commits · e0c06e310c23ebf2bc20f7f4324aec2ec3d34861 · Roger Ferrer / llvm-epi · GitLab

Oct 27, 2020
- [X86] Regenerate popcnt tests. NFCI. · e0c06e31
  Simon Pilgrim authored Oct 27, 2020
  e0c06e31
- [X86] Regenerate xop tests with common prefixes. · fae1ffce
  Simon Pilgrim authored Oct 27, 2020
  
  fae1ffce
- [AMDGPU] Add llvm.amdgcn.div.scale with fneg tests · d028d2b3
  Jay Foad authored Oct 27, 2020
  
  d028d2b3
- [AArch64] Add additional tests for vector inserts with common element. · 548772fe
  Florian Hahn authored Oct 27, 2020
  
  548772fe
- [amdgpu] Enable use of AA during codegen. · 0d092303
  Michael Liao authored Oct 11, 2020
  0d092303
- [X86] Don't crash on CVTPS2PH with wide vector inputs. · 35f7cbf9
  Benjamin Kramer authored Oct 27, 2020
  
  35f7cbf9
- [X86] Regenerate all-ones vector tests with common prefixes. · 3bc58241
  Simon Pilgrim authored Oct 27, 2020
  
  3bc58241
- [X86] Regenerate vector shift tests. NFCI. · 5a855551
  Simon Pilgrim authored Oct 27, 2020
  5a855551
- [TargetLowering] Add i1 condition for bit comparison fold · 5d030800
  Sven van Haastregt authored Oct 27, 2020
  5d030800
- [ARM][AArch64] Add VLDN shuffled interleaving tests. NFC · ad299364
  David Green authored Oct 27, 2020
  
  ad299364
- [X86] Alternate implementation of D88194. · f385823e
  Craig Topper authored Oct 27, 2020
  f385823e
- [X86] Encode global address in small code model · d602e79a
  Wei Wang authored Oct 22, 2020
  d602e79a
- [AMDGPU] Move WQM Pass after MI Scheduler · 7a880ab3
  Carl Ritson authored Oct 27, 2020
  7a880ab3
- [PowerPC] Implement Set Boolean Condition Instructions · 803cc3af
  Amy Kwan authored Oct 26, 2020
  803cc3af
- Explicitly check for entry basic block, rather than relying on MachineBasicBlock::pred_empty. · 0b2f4cdf
  Rahman Lavaee authored Oct 26, 2020
  0b2f4cdf
Oct 26, 2020
- [AMDGPU] Use flat scratch instructions where available · 038d884a
  Stanislav Mekhanoshin authored Oct 21, 2020
  038d884a
- [AArch64] Extend tests for insertelement improvements. · 89485efc
  Florian Hahn authored Oct 26, 2020
  89485efc
- [SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination · 5b742a0c
  Peter Waller authored Oct 19, 2020
  5b742a0c
- Revert "[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination" · 6536d604
  Peter Waller authored Oct 26, 2020
  6536d604
- [SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination · 46044413
  Peter Waller authored Oct 19, 2020
  46044413
- [AArch64] Add 2 cases where insertelement lowering could be improved. · a562dc82
  Florian Hahn authored Oct 26, 2020
  
  a562dc82
- [X86] Use mtriple instead of march in MIR tests · 2030db32
  Simon Pilgrim authored Oct 26, 2020
  
  2030db32
- [VE] Support atomic store · cfefef50
  Kazushi (Jam) Marukawa authored Oct 24, 2020
  cfefef50
- [DAGCombine] Add test case showing incorrect DAGCombine optimization · ffa6d2af
  Fraser Cormack authored Oct 26, 2020
  ffa6d2af
- Try to fix buildbots after d3205bbc · 4afa0778
  Tyker authored Oct 26, 2020
  
  4afa0778
- [Annotation] Allows annotation to carry some additional constant arguments. · d3205bbc
  Tyker authored Oct 26, 2020
  d3205bbc
- [AsmPrinter] Add per BB instruction mix remark. · b2bec7ce
  Florian Hahn authored Oct 26, 2020
  b2bec7ce
- [AMDGPU] Emit new pal metadata by default · a094b4fa
  Sebastian Neubauer authored Oct 23, 2020
  a094b4fa
- [PowerPC] Add test case for pr47830. NFC. · 82150dae
  Kai Luo authored Oct 26, 2020
  
  82150dae
- [VE] Support atomic load · f32992ad
  Kazushi (Jam) Marukawa authored Oct 23, 2020
  f32992ad
- [VE] Support atomic fence · 52f03fe1
  Kazushi (Jam) Marukawa authored Oct 25, 2020
  52f03fe1
- [AMDGPU] Avoid offset register in MUBUF for direct stack object accesses · 5a061041
  Christudasan Devadasan authored Oct 09, 2020
  5a061041
Oct 24, 2020
- [X86] Add a stub for Intel's alderlake. · 39a0d688
  Benjamin Kramer authored Oct 24, 2020
  39a0d688
- [X86] Add a stub for znver3 based on the little public information there is in AMD's manuals · bd2cf96c
  Benjamin Kramer authored Oct 24, 2020
  bd2cf96c
- [LegalizeTypes] Legalize vector rotate operations · 62b17a76
  Simon Pilgrim authored Oct 24, 2020
  62b17a76
- [SystemZ] Define MaxInstLength to have the value of 6. · 7c026a83
  Jonas Paulsson authored Oct 23, 2020
  7c026a83
- [Hexagon] Handle selection between HVX vector predicates · 1b5baa42
  Krzysztof Parzyszek authored Oct 23, 2020
  1b5baa42
Oct 23, 2020
- [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation · a1cc274c
  Cameron McInally authored Oct 23, 2020
  a1cc274c
- [IR] add fn attr for no_stack_protector; prevent inlining on mismatch · b7926ce6
  Nick Desaulniers authored Oct 23, 2020
  b7926ce6
- [PowerPC] Add intrinsics for MMA · edb27912
  Baptiste Saleil authored Oct 13, 2020
  edb27912