Commits · e15770aec4278d6b0f3f400dd54bf45628364db1 · Roger Ferrer / llvm-epi · GitLab

Jul 01, 2019
- AMDGPU/GlobalISel: Custom lower control flow intrinsics · e15770ae
  Matt Arsenault authored Jul 01, 2019
  e15770ae
- AMDGPU/GlobalISel: Handle 16-bit SALU min/max · 4073b337
  Matt Arsenault authored Jul 01, 2019
  4073b337
- AMDGPU/GlobalISel: Lower SALU min/max to cmp+select · 5a7d5111
  Matt Arsenault authored Jul 01, 2019
  5a7d5111
- [X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2) · e20030f6
  Robert Lougher authored Jul 01, 2019
  e20030f6
- AMDGPU/GlobalISel: Add tests for add legalization · 7f8c7209
  Matt Arsenault authored Jul 01, 2019
  7f8c7209
- AMDGPU/GlobalISel: Legalize s16 add/sub/mul · ef59cb69
  Matt Arsenault authored Jul 01, 2019
  ef59cb69
- AMDGPU/GlobalISel: Fix allowing non-boolean conditions for G_SELECT · 9470bb26
  Matt Arsenault authored Jul 01, 2019
  9470bb26
- [NFC][InstCombine] Add tests for "shift direction in bittest" (PR42466) · e6285778
  Roman Lebedev authored Jul 01, 2019
  e6285778
- GlobalISel: Verify G_MERGE_VALUES operand sizes · 03ca176a
  Matt Arsenault authored Jul 01, 2019
  03ca176a
- [GlobalISel]: Allow backends to custom legalize Intrinsics · 1023a2ec
  Aditya Nandakumar authored Jul 01, 2019
  1023a2ec
- AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghalt · b2ea20ee
  Matt Arsenault authored Jul 01, 2019
  b2ea20ee
- AMDGPU/GlobalISel: Legalize s16 fcmp · 40d1faf3
  Matt Arsenault authored Jul 01, 2019
  40d1faf3
- GlobalISel: Implement lower for min/max · 6f74f557
  Matt Arsenault authored Jul 01, 2019
  6f74f557
- AMDGPU/GFX10: implement ds_ordered_count changes · 10c911db
  Nicolai Haehnle authored Jul 01, 2019
  10c911db
- AMDGPU: Support GDS atomics · 4dc3b2bf
  Nicolai Haehnle authored Jul 01, 2019
  4dc3b2bf
- AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap · 1094e6a8
  Matt Arsenault authored Jul 01, 2019
  1094e6a8
- AArch64/GlobalISel: Fix trying to select invalid MIR · 732149b2
  Matt Arsenault authored Jul 01, 2019
  732149b2
- AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelane · 265059ea
  Matt Arsenault authored Jul 01, 2019
  265059ea
- AMDGPU/GlobalISel: Fail instead of assert when selecting loads · a3107278
  Matt Arsenault authored Jul 01, 2019
  a3107278
- AMDGPU/GlobalISel: Complete implementation of G_GEP · 0a52e9d0
  Matt Arsenault authored Jul 01, 2019
  0a52e9d0
- AMDGPU/GlobalISel: Select G_PHI · e1006259
  Matt Arsenault authored Jul 01, 2019
  e1006259
- AMDGPU/GlobalISel: Try to select VOP3 form of add · d810ff25
  Matt Arsenault authored Jul 01, 2019
  d810ff25
- [X86] Add widenSubVector to size in bits helper. NFCI. · e3e38cce
  Simon Pilgrim authored Jul 01, 2019
  e3e38cce
- AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane · 62d64b0c
  Matt Arsenault authored Jul 01, 2019
  62d64b0c
- [docs][llvm-readelf] Expand llvm-readelf documentation · 90c57e00
  James Henderson authored Jul 01, 2019
  90c57e00
- AMDGPU/GlobalISel: Implement select for 32-bit G_ADD · 9e9dd30d
  Tom Stellard authored Jul 01, 2019
  9e9dd30d
- [ARM] Fix MVE_VQxDMLxDH instruction class · 8b2e304b
  Mikhail Maltsev authored Jul 01, 2019
  8b2e304b
- AMDGPU/GlobalISel: Select G_BRCOND for vcc · 2ab25f9c
  Matt Arsenault authored Jul 01, 2019
  2ab25f9c
- [ARM] MVE: support QQPRRegClass and QQQQPRRegClass · 4a9e3f15
  Mikhail Maltsev authored Jul 01, 2019
  4a9e3f15
- Update email address in CODE_OWNERS · 657f8c16
  Krzysztof Parzyszek authored Jul 01, 2019
  657f8c16
- [InstCombine] (Y + ~X) + 1 --> Y - X fold (PR42459) · 04d3d3bb
  Roman Lebedev authored Jul 01, 2019
  04d3d3bb
- [InstCombine] Shift amount reassociation in bittest (PR42399) · 72b8d41c
  Roman Lebedev authored Jul 01, 2019
  72b8d41c
- [Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1) · 5abf80cd
  Krzysztof Parzyszek authored Jul 01, 2019
  5abf80cd
- AMDGPU/GlobalISel: Select G_FRAME_INDEX · cda82f0b
  Matt Arsenault authored Jul 01, 2019
  cda82f0b
- AMDGPU/GFX10: fix scratch resource descriptor · 7cfd99ab
  Nicolai Haehnle authored Jul 01, 2019
  7cfd99ab
- AMDGPU/GlobalISel: Make s16 select legal · fdf36729
  Matt Arsenault authored Jul 01, 2019
  fdf36729
- AMDGPU/GlobalISel: Select G_BRCOND for scc conditions · 6464280e
  Matt Arsenault authored Jul 01, 2019
  6464280e
- AMDGPU/GlobalISel: Tolerate copies with no type set · 1daad91a
  Matt Arsenault authored Jul 01, 2019
  1daad91a
- AMDGPU: Fix tests using the default alloca address space · fb99fc7a
  Matt Arsenault authored Jul 01, 2019
  fb99fc7a
- AMDGPU/GlobalISel: Select src modifiers · 4f64ade0
  Matt Arsenault authored Jul 01, 2019
  4f64ade0