Commits · e299a0814956f2391b4fbc540cc8e6dd2e15d58f · Roger Ferrer / llvm-epi · GitLab

Feb 10, 2020
- [AArch64][SVE] SVE2 intrinsics for character match & histogram generation · e299a081
  Kerry McLaughlin authored Feb 10, 2020
  e299a081
- [AArch64][SVE] Add SVE2 intrinsics for widening DSP operations · 5e1d7bb6
  Kerry McLaughlin authored Feb 10, 2020
  5e1d7bb6
- [CSInfo] Fix the assertions regarding updating the CSInfo · 3a4dc577
  Djordje Todorovic authored Feb 10, 2020
  3a4dc577
Feb 08, 2020
- [GlobalISel][CallLowering] Look through bitcasts from constant function pointers. · 35c63d66
  Amara Emerson authored Feb 07, 2020
  35c63d66
Feb 07, 2020
- [AArch64][GlobalISel] Reland SLT/SGT TBNZ optimization · 609a489e
  Jessica Paquette authored Feb 07, 2020
  609a489e
- [MachineInstr] Add isCandidateForCallSiteEntry predicate · 0d0ef315
  Vedant Kumar authored Feb 06, 2020
  0d0ef315
- [GlobalISel][IRTranslator] Add special case support for ~memory inline asm clobber. · 28d22c2c
  Amara Emerson authored Feb 07, 2020
  28d22c2c
- [AsmPrinter] Print FP constant in hexadecimal form instead · 01edae12
  Jinsong Ji authored Feb 06, 2020
  01edae12
- Revert "[AArch64][GlobalISel] Emit TBNZ with G_BRCOND where the condition is SLT" · 3e5d837c
  Jessica Paquette authored Feb 06, 2020
  3e5d837c
- Revert "[AArch64][GlobalISel] Emit TBZ for SGT cond branches against -1" · df51b685
  Jessica Paquette authored Feb 06, 2020
  df51b685
Feb 06, 2020
- [GlobalISel] Use G_ZEXTLOAD instead of an anyextending load for non-pow-2 legalization. · ac8a12c8
  Amara Emerson authored Feb 06, 2020
  ac8a12c8
- [AArch64][GlobalISel] Emit TBZ for SGT cond branches against -1 · d78cefb1
  Jessica Paquette authored Feb 06, 2020
  d78cefb1
- Revert "[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field" · 6531a78a
  Jeremy Morse authored Feb 05, 2020
  6531a78a
- [AArch64][GlobalISel] Emit TBNZ with G_BRCOND where the condition is SLT · a3738414
  Jessica Paquette authored Feb 05, 2020
  a3738414
- [AArch64][GlobalISel] Fold G_LSHR into test bit calculation · 7212f657
  Jessica Paquette authored Feb 05, 2020
  7212f657
Feb 05, 2020
- GlobalISel: Allow CSE of G_IMPLICIT_DEF · 9087ef07
  Matt Arsenault authored Feb 03, 2020
  9087ef07
- [GlobalISel][AArch64] Fix contract cross-bank copies with SIMD instructions · ce963363
  Shu-Chun Weng authored Feb 04, 2020
  ce963363
- [AArch64][GlobalISel] Fold G_ASHR into TB(N)Z bit calculation · 292f7257
  Jessica Paquette authored Feb 03, 2020
  292f7257
- [AArch64][GlobalISel] Fix one use check in getTestBitReg · a82a28ae
  Jessica Paquette authored Feb 04, 2020
  a82a28ae
Feb 04, 2020
- [X86] -fpatchable-function-entry=N,0: place patch label after ENDBR{32,64} · 8ff86fcf
  Fangrui Song authored Jan 30, 2020
  8ff86fcf
- [ARM][VecReduce] Force expand vector_reduce_fmin · 362d00e0
  David Green authored Feb 04, 2020
  362d00e0
- [AArch64][GlobalISel] Fold G_XOR into TB(N)Z bit calculation · 9effe38b
  Jessica Paquette authored Feb 03, 2020
  9effe38b
Feb 03, 2020
- [AArch64][GlobalISel] Fold G_SHL into TB(N)Z bit calculation · 37910fd0
  Jessica Paquette authored Feb 03, 2020
  37910fd0
- [AArch64][GlobalISel] Walk through G_AND in TB(N)Z bit calculation · 2bd46444
  Jessica Paquette authored Jan 30, 2020
  2bd46444
- [AArch64][GlobalISel] Don't reconvert to p0 in convertPtrAddToAdd(). · b911b990
  Amara Emerson authored Feb 03, 2020
  b911b990
- [FPEnv][AArch64] Add lowering of f128 STRICT_FSETCC · 68cf5748
  John Brawn authored Jan 28, 2020
  68cf5748
- Fix broken invariant · 75d9994a
  Guillaume Chatelet authored Jan 31, 2020
  75d9994a
Feb 02, 2020
- [CodeGenPrepare] Make TargetPassConfig required · 5a56a25b
  Fangrui Song authored Jan 30, 2020
  5a56a25b
Feb 01, 2020
- [PatchableFunction] Use an empty DebugLoc · 5932f7b8
  Fangrui Song authored Feb 01, 2020
  5932f7b8
Jan 31, 2020
- [AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg · b9bf9305
  Jessica Paquette authored Jan 30, 2020
  b9bf9305
- [GlobalISel] Tidy up unnecessary calls to createGenericVirtualRegister · 2a1b5af2
  Jay Foad authored Jan 31, 2020
  2a1b5af2
- [AArch64][SVE] Add SVE2 mla unpredicated intrinsics. · 44a4f5fc
  Danilo Carvalho Grael authored Jan 30, 2020
  44a4f5fc
- [AArch64][SVE] Add remaining SVE2 intrinsics for uniform DSP operations · 69558c84
  Kerry McLaughlin authored Jan 31, 2020
  69558c84
- [GlobalISel][IRTranslator] When translating vector geps, splat the base pointer if required. · 84bd8511
  Amara Emerson authored Jan 30, 2020
  84bd8511
Jan 30, 2020
- [AArch64][GlobalISel] Fold in G_ANYEXT/G_ZEXT into TB(N)Z · c8c987d3
  Jessica Paquette authored Jan 29, 2020
  c8c987d3
- [AArch64] -fpatchable-function-entry=N,0: place patch label after BTI · 06b8e32d
  Fangrui Song authored Jan 29, 2020
  06b8e32d
- [AArch64][SVE] Add remaining SVE2 mla indexed intrinsics. · 0610637a
  Danilo Carvalho Grael authored Jan 29, 2020
  0610637a
- [AArch64][ARM] Always expand ordered vector reductions (PR44600) · 70d345e6
  Nikita Popov authored Jan 21, 2020
  70d345e6
- Drop arm triple from test/CodeGen/AArch64/global-merge-hidden-minsize.ll · 6be9acdf
  Hans Wennborg authored Jan 30, 2020
  6be9acdf
- [FPEnv][AArch64] Add lowering and instruction selection for strict conversions · 0bb9a27c
  John Brawn authored Jan 27, 2020
  0bb9a27c