Commits · e2f6896eef8dcd1d09cf3342aa41b884b7ce9a43 · Roger Ferrer / llvm-epi · GitLab

Nov 08, 2018
- [NFC][BdVer2] Load and store throughput tests: also check sched stats (PR39465) · 38172920
  Roman Lebedev authored Nov 08, 2018
  38172920
- [NFC][BdVer2] Tests for load and store throughput (PR39465) · 2ad16b93
  Roman Lebedev authored Nov 08, 2018
  2ad16b93
Nov 01, 2018
- [llvm-mca] Add extra counters for move elimination in view RegisterFileStatistics. · fe3bc1b9
  Andrea Di Biagio authored Nov 01, 2018
  fe3bc1b9
Oct 27, 2018
- AMD BdVer2 (Piledriver) Initial Scheduler model · a5baf867
  Roman Lebedev authored Oct 27, 2018
  a5baf867
- [NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model · a5192187
  Roman Lebedev authored Oct 27, 2018
  a5192187
Oct 24, 2018
- [MC] Separate masm integer literal lexer support from inline asm · 953bdce6
  Reid Kleckner authored Oct 24, 2018
  953bdce6
Oct 16, 2018
- [X86] Fix Skylake ReadAfterLd for PADDrm etc. · 7d27cfdc
  Simon Pilgrim authored Oct 16, 2018
  7d27cfdc
Oct 12, 2018
- [tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen. · 6eebbe0a
  Andrea Di Biagio authored Oct 12, 2018
  6eebbe0a
Oct 11, 2018
- [llvm-mca][BtVer2] Add tests for optimizable GPR register moves. NFC · 6a0b3195
  Andrea Di Biagio authored Oct 11, 2018
  6a0b3195
Oct 10, 2018
- [llvm-mca][BtVer2] Add two more move-elimination tests. NFC · 1b29ec65
  Andrea Di Biagio authored Oct 10, 2018
  1b29ec65
Oct 05, 2018
- [X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957) · f09fc3bc
  Simon Pilgrim authored Oct 05, 2018
  f09fc3bc
Oct 04, 2018
- [llvm-mca][x86] Add PR36951 ReadAfterLd test case · 6ad03ad3
  Simon Pilgrim authored Oct 04, 2018
  6ad03ad3
- [utils] Ensure that update_mca_test_checks.py writes prefixes in alphabetical order · dee7bfdb
  Greg Bedwell authored Oct 04, 2018
  dee7bfdb
- [llvm-mca][x86] Add tests demonstrating ReadAfterLd delay · 82a3b1c6
  Simon Pilgrim authored Oct 04, 2018
  82a3b1c6
Oct 03, 2018
- [X86][Btver2] Fix MMX PSHUFB schedule · 0b451a29
  Simon Pilgrim authored Oct 03, 2018
  0b451a29
- [llvm-mca] Add support for move elimination in class RegisterFile. · 207e0217
  Andrea Di Biagio authored Oct 03, 2018
  207e0217
- [X86][Btver2] Most RMW instructions don't require an additional uop · c68cc4ef
  Simon Pilgrim authored Oct 03, 2018
  c68cc4ef
- [X86] ALU/ADC RMW instructions should use the WriteRMW sequence class · d1101586
  Simon Pilgrim authored Oct 03, 2018
  d1101586
Oct 02, 2018
- [X86][Btver2] Fix BLENDV and AESDEC schedules · 860cb5c0
  Simon Pilgrim authored Oct 02, 2018
  860cb5c0
Oct 01, 2018
- [X86][Btver2] Fix BT(C|R|S)mr & BT(C|R|S)mi schedule latency + uop counts · e0d20190
  Simon Pilgrim authored Oct 01, 2018
  e0d20190
- [X86][Btver2] Fix BTmr schedule uop counts · 6ddc4e82
  Simon Pilgrim authored Oct 01, 2018
  6ddc4e82
- [X86][Btver2] Fix masked load schedule · a982236e
  Simon Pilgrim authored Oct 01, 2018
  a982236e
- [X86][BtVer2] Teach how to identify zero-idiom VPERM2F128rr instructions. · 24ea1630
  Andrea Di Biagio authored Oct 01, 2018
  24ea1630
- [X86][Sched] Update scheduling information for VZEROALL on HWS, BDW, SKX, SNB. · a933fb23
  Clement Courbet authored Oct 01, 2018
  a933fb23
Sep 30, 2018
- [X86] Fix scheduler class for BTmi instructions · f2108387
  Simon Pilgrim authored Sep 30, 2018
  f2108387
- [LLVM-MCA][X86] Add missing VCMPESTR/VCMPESTR tests · b1108399
  Simon Pilgrim authored Sep 30, 2018
  b1108399
- [LLVM-MCA][X86] Add some AVX512 tests · 20623f23
  Simon Pilgrim authored Sep 30, 2018
  20623f23
- [X86][Btver2] Fix PCmpIStrI/PCmpIStrM schedules · 4f5693ac
  Simon Pilgrim authored Sep 30, 2018
  4f5693ac
Sep 28, 2018
- [llvm-mca] Add a test for zero-idiom VPERM2F128rr. NFC · 6e218d0a
  Andrea Di Biagio authored Sep 28, 2018
  6e218d0a
- [utils] Stricter checking from update_mca_test_checks.py · becbbe03
  Greg Bedwell authored Sep 28, 2018
  becbbe03
- [utils] Allow better identification of matching blocks in update_mca_test_checks.py · 2f528f8c
  Greg Bedwell authored Sep 28, 2018
  2f528f8c
- [X86][Btver2] PSUBS/PSUBUS instructions are zero-idioms · 428c1196
  Simon Pilgrim authored Sep 28, 2018
  428c1196
- [X86][Btver2] Add zero-idiom tests for PSUBS/PSUBUS instructions · 3216fd36
  Simon Pilgrim authored Sep 28, 2018
  3216fd36
- [X86][Btver2] CVTSS2I/CVTSD2I - add missing JFPU0 pipe · 66da1ed2
  Simon Pilgrim authored Sep 28, 2018
  66da1ed2
- [X86][Btver2] Fix BSF/BSR schedule · 17e5981e
  Simon Pilgrim authored Sep 28, 2018
  17e5981e
- [X86][BtVer2] Fix PHMINPOS schedule resources typo · 280af1c7
  Simon Pilgrim authored Sep 28, 2018
  280af1c7
Sep 27, 2018
- [X86][Btver2] (V)MPSADBW instructions take 3uops not 1 · 86c7b07e
  Simon Pilgrim authored Sep 27, 2018
  86c7b07e
- [X86][Btver2] BTC/BTR/BTS instructions take 2uops not 1 · dd744f15
  Simon Pilgrim authored Sep 27, 2018
  dd744f15
- [X86][Btver2] BLSI/BLSMSK/BLSR instructions take 2uops not 1 (same as TZCNT) · c2a88ea6
  Simon Pilgrim authored Sep 27, 2018
  c2a88ea6
- [X86][Btver2] TZCNT instructions take 2uops not 1 · 98f503a3
  Simon Pilgrim authored Sep 27, 2018
  98f503a3