Commits · e3fa2b1eab60342dc882b7b888658b03c472fa2b · Roger Ferrer / llvm-epi · GitLab

Jul 16, 2021
- Revert "[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID" · e3fa2b1e
  Fraser Cormack authored Jul 16, 2021
  e3fa2b1e
- AMDGPU/GlobalISel: Preserve more memory types · 3ceb9229
  Matt Arsenault authored Jul 15, 2021
  
  3ceb9229
- AMDGPU/GlobalISel: Redo kernel argument load handling · 21a0ef8d
  Matt Arsenault authored Jul 15, 2021
  21a0ef8d
- [AArch64][SME] Add load and store instructions · 99eb96f0
  Cullen Rhodes authored Jul 16, 2021
  99eb96f0
- [RISCV] Lower more BUILD_VECTOR sequences to RVV's VID · a6ca88e9
  Fraser Cormack authored Jun 24, 2021
  a6ca88e9
- AMDGPU/GlobalISel: Fix incorrect memory types in test · a81a7a9a
  Matt Arsenault authored Jul 15, 2021
  
  a81a7a9a
- GlobalISel: Track argument pointeriness with arg flags · e91da668
  Matt Arsenault authored Jul 14, 2021
  e91da668
- [PowerPC] Add PowerPC population count, reversed load and store related... · 4eb107cc
  Victor Huang authored Jul 15, 2021
  4eb107cc
Jul 15, 2021
- [X86] Fix handling of maskmovdqu in X32 · a8ad9170
  Harald van Dijk authored Jul 15, 2021
  a8ad9170
- [AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT · 46c8e712
  Jessica Paquette authored Jul 13, 2021
  46c8e712
- [AIX][XCOFF][Bug-Fixed] parse the parameter type of the traceback table · af06f7bc
  zhijian authored Jul 15, 2021
  af06f7bc
- [NVPTX, CUDA] Add .and.popc variant of the b1 MMA instruction. · d774b4aa
  Artem Belevich authored Jul 02, 2021
  d774b4aa
- [M68k][GloballSel] LegalizerInfo implementation · aaccc985
  Sushma Unnibhavi authored Jul 15, 2021
  aaccc985
- [ARM][LowOverheadLoops] Make some stack spills valid for tail predication · ff0ef6a5
  Sam Tebbs authored Jul 05, 2021
  ff0ef6a5
- [PowerPC] Fix popcntb XL Compat Builtin for 32bit · de395660
  Quinn Pham authored Jul 15, 2021
  de395660
- [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated... · aa3df8dd
  Fangrui Song authored Jul 15, 2021
  aa3df8dd
- [GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern · 5da0f9ab
  Jessica Paquette authored Jul 15, 2021
  5da0f9ab
- [AMDGPU] Refine -O0 and -O1 passes. · c46d99e4
  Stanislav Mekhanoshin authored Jul 07, 2021
  c46d99e4
- [DAG] Fold select(cond,binop(x,y),binop(x,z)) -> binop(x,select(cond,y,z)) · 0aece73a
  Simon Pilgrim authored Jul 15, 2021
  0aece73a
- [NVPTX] Tweak fast-math tests to avoid select(binop(x,y),binop(x,z)) fold · 3cc38703
  Simon Pilgrim authored Jul 15, 2021
  3cc38703
- [ARM] Expand types handled in VQDMULH recognition · dad506bd
  David Green authored Jul 15, 2021
  dad506bd
- MachO: don't emit L... private symbols in do_not_dead_strip sections. · 5d7632ee
  Tim Northover authored Jul 15, 2021
  5d7632ee
- [NVPTX] Add selp.f32 checks to select(cond,fpbinop(),fpbinop()) tests · e21663d3
  Simon Pilgrim authored Jul 15, 2021
  e21663d3
- [MIPS] Refresh ashr test checks. NFCI. · d179c432
  Simon Pilgrim authored Jul 15, 2021
  
  d179c432
- [AArch64][GlobalISel] Optimise lowering for some vector types for min/max · 831ee6b0
  Irina Dobrescu authored Jul 09, 2021
  831ee6b0
- [Test] We can benefit from pipelining of ymm load/stores · 69a3acff
  Max Kazantsev authored Jul 15, 2021
  69a3acff
- [2/2][RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs · fa2daaef
  Djordje Todorovic authored Jul 14, 2021
  fa2daaef
- [PowerPC][NFC] add testcase for update-form preparation with non-const increment · 70788052
  Chen Zheng authored Jul 15, 2021
  
  70788052
- [PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand · b9c3941c
  Kai Luo authored Jul 15, 2021
  b9c3941c
- [AMDGPU] Use update_test_checks.py script for annotate kernel features tests. · a7749c3f
  Kuter Dinel authored Jul 13, 2021
  a7749c3f
- [WebAssembly] Codegen for v128.storeX_lane instructions · 4a4229f7
  Thomas Lively authored Jul 14, 2021
  4a4229f7
Jul 14, 2021
- [AArch64] Fix selection of G_UNMERGE <2 x s16> · 0e49c54a
  Jon Roelofs authored Jul 14, 2021
  0e49c54a
- [tests] Stablize tests for possible change in deref semantics · e75a2dfe
  Philip Reames authored Jul 14, 2021
  e75a2dfe
- [AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization · 76b7d343
  Stanislav Mekhanoshin authored Jul 12, 2021
  76b7d343
- [ARM] Move add(VMLALVA(A, X, Y), B) to VMLALVA(add(A, B), X, Y) · 31b8f400
  David Green authored Jul 14, 2021
  31b8f400
- [WebAssembly] Codegen for v128.loadX_lane instructions · 970e0900
  Thomas Lively authored Jul 14, 2021
  970e0900
- [WebAssembly] Remove datalayout strings from llc tests · 122b0220
  Thomas Lively authored Jul 14, 2021
  122b0220
- [ARM] Lower v16i8 -> i64 VMLA reductions. · 338314f9
  David Green authored Jul 14, 2021
  338314f9
- GlobalISel: Handle lowering non-power-of-2 extloads · 47269da5
  Matt Arsenault authored Jun 10, 2021
  
  47269da5
- [AMDGPU] Check llc-pipeline.ll with -match-full-lines -strict-whitespace · 372bb082
  Jay Foad authored Jul 13, 2021
  372bb082