Commits · e53196b1e862902c74d83f0ce6f3578b1326f23d · Roger Ferrer / llvm-epi · GitLab

Sep 26, 2020
- [RISCV] Scheduler description for Bullet · 764c1b7a
  Michael Collison authored Sep 25, 2020
  764c1b7a
- [RISCV] Fix formatting (NFC) · 0291c471
  Evandro Menezes authored Sep 25, 2020
  
  0291c471
Sep 25, 2020
- [RISCV] Merge the pipeline models for Rocket · 1e66e723
  Evandro Menezes authored Sep 17, 2020
  1e66e723
Sep 22, 2020
- [ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop · a3d0dce2
  Meera Nakrani authored Sep 22, 2020
  a3d0dce2
- [RISCV] Do not mandate scheduling for CSR instructions · 394d0201
  Evandro Menezes authored Aug 05, 2020
  394d0201
Sep 21, 2020
- [RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl() · 8cf6778d
  Alex Richardson authored Sep 21, 2020
  8cf6778d
Sep 18, 2020
- [RISCV] Support Shadow Call Stack · 1c466477
  Zhaoshi Zheng authored Mar 26, 2020
  1c466477
Sep 09, 2020
- [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. · e5784ef8
  Amara Emerson authored Aug 28, 2020
  e5784ef8
Sep 08, 2020
- RISCVMatInt.h - remove unnecessary includes. NFCI. · 0dacf3b5
  Simon Pilgrim authored Sep 08, 2020
  0dacf3b5
Sep 03, 2020
- [NFC][RISCV] Simplify pass arg of RISCVMergeBaseOffsetOpt · c5716447
  Ben Shi authored Sep 03, 2020
  c5716447
Aug 28, 2020
- [Attributes] Add a method to check if an Attribute has AttrKind None. Use... · aab90384
  Craig Topper authored Aug 28, 2020
  aab90384
Aug 27, 2020
- [RISC-V] fmv.s/fmv.d should be as cheap as a move · 5ba4d036
  Alex Richardson authored Aug 25, 2020
  5ba4d036
- [RISC-V] Mark C_MV as a move instruction · a11eeb4d
  Alex Richardson authored Aug 25, 2020
  a11eeb4d
- [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move · 2259ce8c
  Alex Richardson authored Aug 25, 2020
  2259ce8c
- [RISCV] add the MC layer support of riscv vector Zvamo extension · 888c02de
  luxufan authored Jul 31, 2020
  888c02de
Aug 21, 2020
- [RISCV] Fix inaccurate annotations on PseudoBRIND · 9e6c09c0
  lewis-revill authored Aug 21, 2020
  9e6c09c0
- [SelectionDAG] Better legalization for FSHL and FSHR · 0819a641
  Jay Foad authored Mar 31, 2020
  0819a641
Aug 20, 2020
- [RISCV] Enable MCCodeEmitter instruction predicate verifier · 3149ec07
  Jessica Clarke authored Aug 20, 2020
  3149ec07
Aug 19, 2020
- [RISCV] add the assemble and disassemble support of Zvlsseg instructions · 6c5039a1
  luxufan authored Jul 23, 2020
  6c5039a1
Aug 17, 2020
- [RISCV] Enable the use of the old mucounteren name · 3f7068ad
  Sam Elliott authored Aug 17, 2020
  3f7068ad
- [RISCV] Indirect branch generation in position independent code · 5f9ecc5d
  Sam Elliott authored Aug 17, 2020
  5f9ecc5d
Aug 15, 2020
- [X86][MC][Target] Initial backend support a tune CPU to support -mtune · c7a0b268
  Craig Topper authored Aug 14, 2020
  c7a0b268
Aug 03, 2020
- [RISCV] eliminate the repetition declare of SDLoc DL · a96921af
  StephenFan authored Jul 31, 2020
  a96921af
Aug 01, 2020
- Upgrade MC to v0.9. · 47a4a27f
  Hsiangkai Wang authored May 21, 2020
  47a4a27f
Jul 20, 2020
- [NFC] remove unused includes of SelectionDAGISel.h · ca1e69a6
  Yuanfang Chen authored Jul 10, 2020
  
  ca1e69a6
Jul 16, 2020
- [RISCV] Add support for -mcpu option. · 294d1eae
  Zakk Chen authored Jul 16, 2020
  294d1eae
Jul 15, 2020
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions · c9c955ad
  lewis-revill authored Jul 15, 2020
  c9c955ad
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions · d4be3337
  lewis-revill authored Jul 15, 2020
  d4be3337
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions · 6144f0a1
  lewis-revill authored Jul 15, 2020
  6144f0a1
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions · 31b52b43
  lewis-revill authored Jul 15, 2020
  31b52b43
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions · e2692f0e
  lewis-revill authored Jul 15, 2020
  e2692f0e
- [RISCV] Duplicate pseudo expansion comment to RISCVMCCodeEmitter · 2dc16fbd
  Jessica Clarke authored Jul 15, 2020
  2dc16fbd
- [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos · 3382c243
  Jessica Clarke authored Jul 15, 2020
  3382c243
Jul 14, 2020
- [RISCV] Fix isStoreToStackSlot · 0cbdd2a8
  Roger Ferrer authored Jul 14, 2020
  0cbdd2a8
- Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" · 1d15bbb9
  Sam Elliott authored Jul 14, 2020
  1d15bbb9
Jul 13, 2020
- RISCV: Avoid GlobalISel build break in a future patch · db091e12
  Matt Arsenault authored Jul 13, 2020
  db091e12
- [MC][RISCV] Set UseIntegratedAssembler to true · 4d5fd0ee
  Fangrui Song authored Jul 12, 2020
  4d5fd0ee
Jul 10, 2020
- [RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive · 04b9a46c
  Zakk Chen authored Apr 30, 2020
  04b9a46c
Jul 09, 2020
- [RISCV] Avoid Splitting MBB in RISCVExpandPseudo · 97106f9d
  Sam Elliott authored Jul 09, 2020
  97106f9d
Jul 08, 2020
- [RISCV] optimize addition with a pair of (addi imm) · 1e9d0811
  Ben Shi authored Jul 07, 2020
  1e9d0811