Commits · e5400f8a6e601729da4aa6706cda3db37a06bf13 · Roger Ferrer / llvm-epi · GitLab

Nov 07, 2017
- [DWARFv5] Support DW_FORM_strp in the .debug_line header. · e5400f8a
  Paul Robinson authored Nov 07, 2017
  e5400f8a
- Recommit r317510 "[InstCombine] Pull shifts through a select plus binop with constant" · 7dd4d324
  Craig Topper authored Nov 07, 2017
  7dd4d324
- [InstCombine] Update stale comment. NFC · 386fc251
  Craig Topper authored Nov 07, 2017
  386fc251
- [Hexagon] Make a test more flexible in HexagonLoopIdiomRecognition · 385a4e04
  Krzysztof Parzyszek authored Nov 07, 2017
  385a4e04
- [AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZ · b9368108
  Florian Hahn authored Nov 07, 2017
  b9368108
- [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support · 91f11e5a
  Florian Hahn authored Nov 07, 2017
  91f11e5a
- [SelectionDAG] Fix typo in comment. NFC · 41bf2407
  Craig Topper authored Nov 07, 2017
  41bf2407
- [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. · d825bbdc
  Florian Hahn authored Nov 07, 2017
  d825bbdc
- Reland "Correct dwarf unwind information in function epilogue for X86" · e2a585dd
  Petar Jovanovic authored Nov 07, 2017
  e2a585dd
- Silence MSVC error C2398 · d5b7a00f
  Kristof Beyls authored Nov 07, 2017
  d5b7a00f
- [SLP] Fix PR35047: Fix default cost model for cast op in X86. · e25a6fd3
  Alexey Bataev authored Nov 07, 2017
  e25a6fd3
- Mark intentional fall-through with LLVM_FALLTHROUGH. · 78aa4b28
  Kristof Beyls authored Nov 07, 2017
  78aa4b28
- Add a -D flag to FileCheck to define variables · 46e1fd61
  Alexander Richardson authored Nov 07, 2017
  46e1fd61
- [X86] Regenerate select tests · 9a6b720f
  Simon Pilgrim authored Nov 07, 2017
  9a6b720f
- [AArch64][SVE] Asm: Replace 'IsVector' by 'RegKind' in AArch64AsmParser (NFC) · c4422247
  Florian Hahn authored Nov 07, 2017
  c4422247
- Silence C4715 warning from MSVC (NFC). · 178818ba
  Kristof Beyls authored Nov 07, 2017
  178818ba
- [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors · 603c6455
  Florian Hahn authored Nov 07, 2017
  603c6455
- [GlobalISel] Enable legalizing non-power-of-2 sized types. · af9814a1
  Kristof Beyls authored Nov 07, 2017
  af9814a1
- [CGP] Disable Select instruction handling in optimizeMemoryInst. NFC · 36520029
  Serguei Katkov authored Nov 07, 2017
  36520029
- [docs][ARM] Add HowTo for cross compiling and testing compiler-rt builtins · 7411da55
  Peter Smith authored Nov 07, 2017
  7411da55
- [X86] Don't clobber reserved registers with stack adjustments · c02b237e
  Bjorn Steinbrink authored Nov 07, 2017
  c02b237e
- [X86] Add patterns to fold a 64-bit load into the EVEX vcvtph2ps instructions. · e7fb3002
  Craig Topper authored Nov 07, 2017
  e7fb3002
- [X86] Add patterns for folding a v16i8 with the VEX vcvtph2ps intrinsics. · 0231b1d4
  Craig Topper authored Nov 07, 2017
  0231b1d4
- [X86] Add a test for a 128-bit vector load feeding a cvtph2ps intrinsic. · 65fc5332
  Craig Topper authored Nov 07, 2017
  65fc5332
- [X86] Remove alignment from a load in the f16c intrinsic test. The alignment... · 8942b33f
  Craig Topper authored Nov 07, 2017
  8942b33f
- [X86] Add support for using EVEX instructions for the legacy vcvtph2ps intrinsics. · cf8e6d0a
  Craig Topper authored Nov 07, 2017
  cf8e6d0a
- [X86] Add AVX512VL command line to f16c intrinsic test to show missed EVEX... · 75510dd6
  Craig Topper authored Nov 07, 2017
  75510dd6
- [X86] Use IMPLICIT_DEF in VEX/EVEX vcvtss2sd/vcvtsd2ss patterns instead of a COPY_TO_REGCLASS. · afc3c820
  Craig Topper authored Nov 07, 2017
  afc3c820
- [X86] Remove 'Requires' from instructions with no patterns. NFC · 4ad81b51
  Craig Topper authored Nov 07, 2017
  4ad81b51
- [Support/UNIX] posix_fallocate() can fail with EINVAL. · 1f465aa6
  Davide Italiano authored Nov 07, 2017
  1f465aa6
- Make DIExpression::createFragmentExpression() return an Optional. · 25a09dd4
  Adrian Prantl authored Nov 07, 2017
  25a09dd4
- [XRay] Minimal tool to convert xray traces to Chrome's Trace Event Format. · 42427995
  Keith Wyss authored Nov 07, 2017
  42427995
- [IPO/LowerTypesTest] Skip blockaddress(es) when replacing uses. · 1a46affb
  Davide Italiano authored Nov 07, 2017
  1a46affb
- AMDGPU: Remove redundant combine · 6119f800
  Matt Arsenault authored Nov 07, 2017
  6119f800
- [DebugInfo] Unify logic to merge DILocations. NFC. · 2b881f56
  Vedant Kumar authored Nov 06, 2017
  2b881f56
- [Support][Chrono] Use explicit cast of text output of time values. · 8bdbff37
  Simon Dardis authored Nov 06, 2017
  8bdbff37
Nov 06, 2017
- InstCombine: salvage the debug info of DCE'ed add instructions. · 182f9fea
  Adrian Prantl authored Nov 06, 2017
  182f9fea
- [X86] Make FeatureAVX512 imply FeatureF16C. · 428a4e63
  Craig Topper authored Nov 06, 2017
  428a4e63
- [X86] Make FeatureAVX512 imply FeatureFMA. · cb6c3861
  Craig Topper authored Nov 06, 2017
  cb6c3861
- [ValueTracking] readonly (const) is a requirement for converting sqrt to llvm.sqrt; nnan is not · 86d24f16
  Sanjay Patel authored Nov 06, 2017
  86d24f16