Commits · e5be543a55986e353d40d79702eef5cff3934348 · Roger Ferrer / llvm-epi · GitLab

Aug 02, 2019
- Finish moving TargetRegisterInfo::isVirtualRegister() and friends to... · 2bea69bf
  Daniel Sanders authored Aug 01, 2019
  2bea69bf
Jun 24, 2019
- CodeGen: Introduce a class for registers · e3a676e9
  Matt Arsenault authored Jun 24, 2019
  e3a676e9
Jan 19, 2019
- Update the file headers across all of the LLVM projects in the monorepo · 2946cd70
  Chandler Carruth authored Jan 19, 2019
  2946cd70
Jun 29, 2018
- AMDGPU: Separate R600 and GCN TableGen files · c5a154db
  Tom Stellard authored Jun 28, 2018
  c5a154db
May 22, 2018
- AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers · 44b30b45
  Tom Stellard authored May 22, 2018
  44b30b45
May 01, 2018
- Remove \brief commands from doxygen comments. · 5f8f34e4
  Adrian Prantl authored May 01, 2018
  5f8f34e4
Jan 24, 2018
- [AMDGPU] Make sure all super regs of reserved regs are marked reserved. · c4796d47
  Geoff Berry authored Jan 24, 2018
  c4796d47
May 17, 2017
- AMDGPU: Start defining a calling convention · 2b1f9aa5
  Matt Arsenault authored May 17, 2017
  2b1f9aa5
Jul 09, 2016
- AMDGPU: Move R600 only pieces into R600 classes · 52a4d9b4
  Matt Arsenault authored Jul 09, 2016
  52a4d9b4
Jun 24, 2016
- AMDGPU: Cleanup subtarget handling. · 43e92fe3
  Matt Arsenault authored Jun 24, 2016
  43e92fe3
Jun 13, 2015
- R600 -> AMDGPU rename · 45bb48ea
  Tom Stellard authored Jun 13, 2015
  45bb48ea
Mar 11, 2015
- Remove the need to cache the subtarget in the R600 TargetRegisterInfo · 6c5b511b
  Eric Christopher authored Mar 11, 2015
  6c5b511b
Jun 13, 2014
- R600: Remove AMDIL instruction and register definitions · bc5b5370
  Tom Stellard authored Jun 13, 2014
  bc5b5370
- R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget · 2e59a45f
  Tom Stellard authored Jun 13, 2014
  2e59a45f
Nov 15, 2013
- R600: Fix scheduling of instructions that use the LDS output queue · 8f9fc207
  Tom Stellard authored Nov 15, 2013
  8f9fc207
Nov 14, 2013
- R600/SI: Add support for private address space load/store · 81d871de
  Tom Stellard authored Nov 13, 2013
  81d871de
Oct 22, 2013
- R600: Simplify handling of private address space · 26a3b67b
  Tom Stellard authored Oct 22, 2013
  26a3b67b
Aug 15, 2013
- R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 · 8e5da413
  Tom Stellard authored Aug 14, 2013
  8e5da413
Jun 07, 2013
- Don't cache the instruction and register info from the TargetMachine, because · 37e9adb0
  Bill Wendling authored Jun 07, 2013
  37e9adb0
May 17, 2013
- R600: Use bottom up scheduling algorithm · 3d5118ca
  Vincent Lejeune authored May 17, 2013
  3d5118ca
Feb 19, 2013
- R600: Mark all members of the TRegMem register class as reserved · a24a5167
  Tom Stellard authored Feb 19, 2013
  a24a5167
Feb 07, 2013
- R600: Consolidate sub register indices. · 9355b221
  Tom Stellard authored Feb 07, 2013
  9355b221
Feb 06, 2013
- R600: Support for indirect addressing v4 · f3b2a1e8
  Tom Stellard authored Feb 06, 2013
  f3b2a1e8
Feb 05, 2013
- R600: improve inputs/interpolation handling · 41afe6a6
  Tom Stellard authored Feb 05, 2013
  41afe6a6
Jan 23, 2013
- R600: rework handling of the constants · 365366f9
  Tom Stellard authored Jan 23, 2013
  365366f9
Dec 11, 2012
- Add R600 backend · 75aadc28
  Tom Stellard authored Dec 11, 2012
  75aadc28