Commits · e5f022cad99abb39d4f66b151a4a31a4ac063aff · Roger Ferrer / llvm-epi · GitLab

Jul 14, 2020
- [AMDGPU][NFC] Tidy sgpr-control-flow.ll whitespace · e5f022ca
  Carl Ritson authored Jul 14, 2020
  e5f022ca
- [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations · 74c14202
  Carl Ritson authored Jul 14, 2020
  74c14202
- [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang · 62f5ba62
  Amy Kwan authored Jul 13, 2020
  62f5ba62
- [AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy · 64eb3a49
  Amara Emerson authored Jun 17, 2020
  64eb3a49
- [PowerPC] Generate CFI directives when probing in prologue · d4e7d126
  Kai Luo authored Jul 13, 2020
  d4e7d126
- [PowerPC] Fix combineVectorShuffle regression after D77448 · eafe7c14
  Fangrui Song authored Jul 13, 2020
  eafe7c14
- Check output in test/CodeGen/Generic/MIRStripDebug/no-metadata-present.mir, NFC · 528a1c56
  Vedant Kumar authored Jul 13, 2020
  
  528a1c56
Jul 13, 2020
- [debugify] Add targeted test for 2fa656cd , NFC · e51c7fb8
  Vedant Kumar authored Jul 13, 2020
  e51c7fb8
- GlobalISel: Implement fewerElementsVector for saturating add/sub · 23ec773d
  Matt Arsenault authored Jul 12, 2020
  
  23ec773d
- GlobalISel: Implement widenScalar for saturating add/sub · 6a8c11a1
  Matt Arsenault authored Jul 12, 2020
  6a8c11a1
- AMDGPU/GlobalISel: Add baseline add/sub sat legalization tests · c0ee2d74
  Matt Arsenault authored Jul 12, 2020
  
  c0ee2d74
- AMDGPU/GlobalISel: Add tests for 96-bit add/sub/mul · 87f8a4f9
  Matt Arsenault authored Jul 12, 2020
  87f8a4f9
- [PGO][PGSO] Add profile guided size optimization to X86ISelDAGToDAG. · fb558cca
  Hiroshi Yamauchi authored Jul 07, 2020
  fb558cca
- [PGO][PGSO] Add profile guided size optimization to the X86 LEA fixup. · 153a0b89
  Hiroshi Yamauchi authored Jul 07, 2020
  153a0b89
- [DAGCombiner] rot i16 X, 8 --> bswap X · 8779b114
  Sanjay Patel authored Jul 13, 2020
  8779b114
- [x86] add tests for bswap/rotate; NFC · 69fff1fc
  Sanjay Patel authored Jul 13, 2020
  
  69fff1fc
- [ARM][NFC] More detailed vbsl checks in ARM & Thumb2 tests. · 8f7d3430
  Pavel Iliin authored Jul 13, 2020
  
  8f7d3430
- [DAGCombiner] allow load/store merging if pairs can be rotated into place · 2df46a57
  Sanjay Patel authored Jul 13, 2020
  2df46a57
- Revert "[DAGCombiner] allow load/store merging if pairs can be rotated into place" · f1bbf3ac
  Sanjay Patel authored Jul 13, 2020
  f1bbf3ac
- [DAGCombiner] allow load/store merging if pairs can be rotated into place · 591a3af5
  Sanjay Patel authored Jul 13, 2020
  591a3af5
- [ARM][MVE] Refactor option -disable-mve-tail-predication · 595270ae
  Sjoerd Meijer authored Jul 13, 2020
  595270ae
- [AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot. · 38998cfa
  Mirko Brkusanin authored Jul 13, 2020
  38998cfa
- [SVE] Ensure fixed length vector fptrunc operations bigger than NEON are not considered legal. · 319a97b5
  Paul Walker authored Jul 13, 2020
  319a97b5
- [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot · ce23e541
  Mirko Brkusanin authored Jul 13, 2020
  ce23e541
- [GlobalISel][InlineAsm] Fix buildCopy for inputs · fd85b40a
  Petar Avramovic authored Jul 13, 2020
  fd85b40a
- [PowerPC] Enhance tests for D83276. NFC. · ac8dc526
  Kai Luo authored Jul 13, 2020
  
  ac8dc526
- [PowerPC] Support constrained conversion in SPE target · b6912c87
  Qiu Chaofan authored Jul 13, 2020
  b6912c87
- [MC][RISCV] Set UseIntegratedAssembler to true · 4d5fd0ee
  Fangrui Song authored Jul 12, 2020
  4d5fd0ee
Jul 12, 2020
- [X86] Consistently use 128 as the PSHUFB/VPPERM index for zero · f8f007e3
  Craig Topper authored Jul 12, 2020
  f8f007e3
- BPF: permit .maps section variables with typedef type · 152a9fef
  Yonghong Song authored Jul 11, 2020
  152a9fef
- [DAGCombiner] tighten fast-math constraints for fma fold · 39009a82
  Sanjay Patel authored Jul 12, 2020
  39009a82
Jul 11, 2020
- [X86] Add test cases for missed opportunities to use vpternlog due to a... · 47872adf
  Craig Topper authored Jul 11, 2020
  47872adf
- [AMDGPU] Move LowerSwitch pass to CodeGenPrepare. · d7a05698
  Christudasan Devadasan authored Jul 11, 2020
  d7a05698
- [X86][MMX] Optimize MMX shift intrinsics. · e6280925
  Wang, Pengfei authored Jul 10, 2020
  e6280925
- [PowerPC][MachinePipeliner] Enable pipeliner if hasInstrSchedModel · 3e3acc1c
  Jinsong Ji authored Jul 11, 2020
  3e3acc1c
- [RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation · 28acaf84
  Ben Shi authored Jul 10, 2020
  28acaf84
- [WebAssembly] Prefer v128.const for constant splats · b59c6fca
  Thomas Lively authored Jul 10, 2020
  b59c6fca
- AMDGPU: Remove .value_type from kernel metadata · 31f4e43f
  Matt Arsenault authored Jun 29, 2020
  31f4e43f
- [X86] Add isel patterns for matching broadcast vpternlog if the ternlog and... · 122a45fb
  Craig Topper authored Jul 10, 2020
  122a45fb
Jul 10, 2020
- [PowerPC] Enable default support of quad precision operations · 90b1a710
  Lei Huang authored Jul 08, 2020
  90b1a710