Commits · e660fdd953b494f6b4f6b41782a47a5eb367b333 · Roger Ferrer / llvm-epi · GitLab

Jan 23, 2012
- Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] · e660fdd9
  Devang Patel authored Jan 23, 2012
  e660fdd9
- Intel syntax: Parse segment registers. · 880bc164
  Devang Patel authored Jan 23, 2012
  880bc164
- Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. · edd1d0ac
  Craig Topper authored Jan 23, 2012
  edd1d0ac
- Update more places to use target specific nodes for vector shifts instead of intrinsics. · 6b90c5d0
  Craig Topper authored Jan 23, 2012
  6b90c5d0
- Custom lower vector shift intrinsics to target specific nodes and remove the... · 5e80db4e
  Craig Topper authored Jan 23, 2012
  5e80db4e
- Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32... · 20c98df3
  Craig Topper authored Jan 23, 2012
  20c98df3
- Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. · 0b7ad76b
  Craig Topper authored Jan 22, 2012
  0b7ad76b
Jan 22, 2012
- Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86... · bd488437
  Craig Topper authored Jan 22, 2012
  bd488437
- Add target specific ISD node types for SSE/AVX vector shuffle instructions and... · 09462641
  Craig Topper authored Jan 22, 2012
  09462641
- Make code a little less verbose. · a4ed5246
  Craig Topper authored Jan 22, 2012
  a4ed5246
- Remove unused X86 ISD node type defines. · cb3433cd
  Craig Topper authored Jan 22, 2012
  cb3433cd
- Move some vector shift patterns into their instruction definitions. · 123adfa0
  Craig Topper authored Jan 22, 2012
  123adfa0
Jan 21, 2012
- Add memory patterns for some of the fp<->integer conversion instructions. Fold... · dcaa5fbd
  Craig Topper authored Jan 21, 2012
  dcaa5fbd
- Remove unused variables. · 5cff13a3
  Benjamin Kramer authored Jan 21, 2012
  5cff13a3
- Fix PR11819 introduced by r148537. I'd commit the test case, but the generated... · 39bc1e4d
  Craig Topper authored Jan 21, 2012
  39bc1e4d
Jan 20, 2012
- Intel syntax: Robustify register parsing. · ce6a2ca8
  Devang Patel authored Jan 20, 2012
  ce6a2ca8
- More dead code removal (using -Wunreachable-code) · 46a9f016
  David Blaikie authored Jan 20, 2012
  46a9f016
- Intel syntax: Parse ... PTR [-8] · d0930fff
  Devang Patel authored Jan 20, 2012
  d0930fff
- Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. · f36613cb
  Devang Patel authored Jan 20, 2012
  f36613cb
- Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As... · a4094790
  Craig Topper authored Jan 20, 2012
  a4094790
- Add support for selecting 256-bit PALIGNR. · 3469212c
  Craig Topper authored Jan 20, 2012
  3469212c
- Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff. · 32c7c25d
  Eli Friedman authored Jan 20, 2012
  32c7c25d
Jan 19, 2012
- Post process 'and', 'sub' instructions and select better encoding, if available. · f83dcfd0
  Devang Patel authored Jan 19, 2012
  f83dcfd0
- Intel syntax: There is no need to create unary expr for simple negative displacement. · 2529dd9e
  Devang Patel authored Jan 19, 2012
  2529dd9e
- Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. · 4a62ff9b
  Devang Patel authored Jan 19, 2012
  4a62ff9b
- Folding table additions and fixes for AVX. · a875b7cc
  Craig Topper authored Jan 19, 2012
  a875b7cc
- Merge 128-bit and 256-bit SHUFPS/SHUFPD handling. · 80576e8d
  Craig Topper authored Jan 19, 2012
  80576e8d
- Add a TargetOption for disabling tail calls. · ecc0084f
  Nick Lewycky authored Jan 19, 2012
  ecc0084f
- Add experimental -x86-use-regmask command line option. · ff482f73
  Jakob Stoklund Olesen authored Jan 18, 2012
  ff482f73
- Ignore register mask operands when lowering instructions to MC. · f1fb1d23
  Jakob Stoklund Olesen authored Jan 18, 2012
  f1fb1d23
Jan 18, 2012
- Process instructions after match to select alternative encoding which may be more desirable. · de47cced
  Devang Patel authored Jan 18, 2012
  de47cced
- Tidy up. MCAsmBackend naming conventions. · aba3de99
  Jim Grosbach authored Jan 18, 2012
  aba3de99
- Add a CoveredBySubRegs property to Register descriptions. · f43b5995
  Jakob Stoklund Olesen authored Jan 18, 2012
  f43b5995
Jan 17, 2012
- Move X86 callee saved register lists to the X86CallConv .td file. · d51a710b
  Jakob Stoklund Olesen authored Jan 17, 2012
  d51a710b
- Intel syntax: Fix parser match class to check memory operand size. · c9ed5187
  Devang Patel authored Jan 17, 2012
  c9ed5187
- Intel syntax: Parse "BYTE PTR [RDX + RCX]" · a7143b6a
  Devang Patel authored Jan 17, 2012
  a7143b6a
- Untabify. · 2ed67186
  Devang Patel authored Jan 17, 2012
  2ed67186
- Intel syntax: Do not unncessarily create plus expression for memory operand displacement. · 8b39be79
  Devang Patel authored Jan 17, 2012
  8b39be79
- Intel syntax: Robustify memory operand parsing. · 41b9ddeb
  Devang Patel authored Jan 17, 2012
  41b9ddeb
- Fix warning. · 86c3807b
  Nadav Rotem authored Jan 17, 2012
  86c3807b