Commits · e72730ee3a5740c3a8be9db03eb30f00ef9b53e1 · Roger Ferrer / llvm-epi · GitLab

Mar 27, 2020
- [InstCombine] add tests for FP cast+bitcast signbit checks; NFC · e72730ee
  Sanjay Patel authored Mar 27, 2020
  e72730ee
- CodeGen: Add -denormal-fp-math-f32 flag · a8cc9047
  Matt Arsenault authored Dec 04, 2019
  a8cc9047
- [AMDGPU] Fix getEUsPerCU for gfx10 in CU mode · a6dfd827
  Jay Foad authored Mar 26, 2020
  a6dfd827
- [MC][X86] Make .reloc support arbitrary relocation types · 152d14da
  Fangrui Song authored Mar 27, 2020
  152d14da
- Fix line endings in test · 0fd8030b
  Matt Arsenault authored Mar 27, 2020
  
  0fd8030b
- AMDGPU: Stop setting attributes based on TargetOptions · 348735b7
  Matt Arsenault authored Dec 05, 2019
  348735b7
- [MC][AArch64] Make .reloc support arbitrary relocation types · 34d77516
  Fangrui Song authored Mar 24, 2020
  34d77516
- [MC][ARM] Make .reloc support arbitrary relocation types · c3895261
  Fangrui Song authored Mar 24, 2020
  c3895261
- [X86] Don't form masked instructions if the operation has an additional user. · cdd1cd71
  Craig Topper authored Mar 27, 2020
  cdd1cd71
- [X86][SSE] Add some additional v8i16 'truncation' style shuffle tests · 763c8730
  Simon Pilgrim authored Mar 27, 2020
  
  763c8730
- Export Segment.IsGapRegion to JSON · aa0be69e
  Dennis Felsing authored Mar 27, 2020
  aa0be69e
- [llvm-objdump][XCOFF][AIX] Implement -r option · d60d7d69
  jasonliu authored Mar 27, 2020
  d60d7d69
- [ARM][LowOverheadLoops] DoubleWidthResult instructions canGenerateZeros · d7084fa3
  Sam Parker authored Mar 27, 2020
  d7084fa3
- [InstCombine][X86] Add repeated ops demanded elts tests for SSE intrinsics (PR24523) · f4f4a8bf
  Simon Pilgrim authored Mar 27, 2020
  
  f4f4a8bf
- [InstCombine][X86] Regenerate SSE2 tests · ec3bb6c3
  Simon Pilgrim authored Mar 27, 2020
  
  ec3bb6c3
- [Alignment] Fix overaligning bug · e2ef6127
  Guillaume Chatelet authored Mar 27, 2020
  e2ef6127
- [ARM] Fix MVE VCMPr f16 pattern · 8689f98e
  David Green authored Mar 27, 2020
  8689f98e
- [llvm-readobj] - Fix a crash when DT_STRTAB is broken. · 30c1f9a5
  Georgii Rymar authored Mar 24, 2020
  30c1f9a5
- [X86][MC] Fix the bug for prefix padding support · 1fb4f99a
  Shengchen Kan authored Mar 17, 2020
  1fb4f99a
- [PowerPC] Fix test for PR45297 to adapt build without asserts. NFC. · 26b46b67
  Kai Luo authored Mar 27, 2020
  
  26b46b67
- [PowerPC] Enhance test for PR45297. NFC. · 351b1923
  Kai Luo authored Mar 27, 2020
  
  351b1923
- [DAGCombine] Add basic optimizations for FREEZE in SelDag · 1bcc500b
  Juneyoung Lee authored Mar 24, 2020
  1bcc500b
- [WebAssembly] Fix the order of destructors in the LowerGlobalDtors pass. · d865437d
  Dan Gohman authored Nov 24, 2019
  d865437d
Mar 26, 2020
- [AMDGPU] Propagate amdgpu-waves-per-eu to callees · 4c4b7184
  Stanislav Mekhanoshin authored Mar 25, 2020
  4c4b7184
- [X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG. · 9f7d4150
  Craig Topper authored Mar 26, 2020
  9f7d4150
- [X86] Prefer PACKUS(AND(),AND()) to SHUFFLE(PSHUFB(),PSHUFB()) on all targets · ad36491e
  Simon Pilgrim authored Mar 26, 2020
  ad36491e
- [X86] lowerV16I8Shuffle - create v8i16 mask for PACKUS(AND(),AND()) patterns. · 39a52a19
  Simon Pilgrim authored Mar 26, 2020
  39a52a19
- [AIX] discard the label in the csect of function description and use qualname for linkage · fdfe411e
  diggerlin authored Mar 26, 2020
  fdfe411e
- [InstCombine] add shuffle-with-bitcast-operand tests; NFC · 5237262f
  Sanjay Patel authored Mar 25, 2020
  
  5237262f
- [InstCombine] Fix Incorrect fold of ashr+xor -> lshr w/ vectors · 7a89a5d8
  Jon Roelofs authored Mar 25, 2020
  7a89a5d8
- [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32 · 459e8e94
  Justin Hibbits authored Mar 23, 2020
  459e8e94
- [X86][SSE] Prefer PACKUS(AND(),AND()) to SHUFFLE(PSHUFB(),PSHUFB()) on pre-AVX2 targets · 9d1721ce
  Simon Pilgrim authored Mar 26, 2020
  9d1721ce
- [PPCInstPrinter] Change printBranchOperand(calltarget) to print the target... · 3eef4740
  Fangrui Song authored Mar 22, 2020
  3eef4740
- [X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form · 87de9a07
  Fangrui Song authored Mar 22, 2020
  87de9a07
- [Legalizer] Fix some flags miss in vector results · 172456c7
  Qiu Chaofan authored Mar 26, 2020
  172456c7
- [NFC] Create X86 subdirectory for indvar tests · db8a3c42
  Sam Parker authored Mar 26, 2020
  db8a3c42
- [X86][SSE] getFauxShuffleMask - peek through TRUNCATE/AEXT/ZEXT for... · e30d29eb
  Simon Pilgrim authored Mar 26, 2020
  e30d29eb
- [PowerPC] Remove the repeated definition for some InstAlias for mtspr/mfspr · 4673699a
  Kang Zhang authored Mar 26, 2020
  4673699a
- [AArch64][SVE] Implement structured store intrinsics · 9086db70
  Cullen Rhodes authored Mar 25, 2020
  9086db70
- [PATCH] [ARM] ARMv8.6-a command-line + BFloat16 Asm Support · 71ae267d
  Ties Stuij authored Mar 26, 2020
  71ae267d