Commits · e7b4d209987ab94f3ec8f88256257d02dff898a4 · Roger Ferrer / llvm-epi · GitLab

Sep 05, 2019
- AMDGPU: Add intrinsics for address space identification · f581d575
  Matt Arsenault authored Sep 05, 2019
  f581d575
- AMDGPU/GlobalISel: Restore insert point when getting aperture · 69b1a2ae
  Matt Arsenault authored Sep 05, 2019
  69b1a2ae
- AMDGPU/GlobalISel: Fix placeholder value used for addrspacecast · 25156ae7
  Matt Arsenault authored Sep 05, 2019
  25156ae7
- AMDGPU/GlobalISel: Fix assert on load from constant address · d51a3746
  Matt Arsenault authored Sep 05, 2019
  d51a3746
- [AArch64][GlobalISel] Teach AArch64CallLowering to handle basic sibling calls · b78324fc
  Jessica Paquette authored Sep 04, 2019
  b78324fc
Sep 04, 2019
- AMDGPU/GlobalISel: Select G_BITREVERSE · 2df41a8e
  Matt Arsenault authored Sep 04, 2019
  2df41a8e
- GlobalISel: Add basic legalization for G_BITREVERSE · 5ff310e2
  Matt Arsenault authored Sep 04, 2019
  5ff310e2
- AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9 · 84489b34
  Matt Arsenault authored Sep 04, 2019
  84489b34
- AMDGPU/GlobalISel: Make 16-bit constants legal · d9af712d
  Matt Arsenault authored Sep 04, 2019
  d9af712d
- [Hexagon] Improve generated code for test-if-bit-clear, one more time · 08a09822
  Krzysztof Parzyszek authored Sep 04, 2019
  08a09822
- [ARM][ParallelDSP] SExt mul for accumulation · fea53223
  Sam Parker authored Sep 04, 2019
  fea53223
- [RISCV] Enable tail call opt for variadic function · b77aa1d2
  Jim Lin authored Sep 04, 2019
  b77aa1d2
- Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn · 3fa07dee
  Reid Kleckner authored Sep 03, 2019
  3fa07dee
- [WebAssembly] Compare functions by names in Emscripten Sjlj · 49e7ee4d
  Heejin Ahn authored Sep 03, 2019
  49e7ee4d
Sep 03, 2019
- [AArch64][GlobalISel] Legalize 128 bit divisions to libcalls. · 2a2c25ba
  Amara Emerson authored Sep 03, 2019
  2a2c25ba
- [GlobalISel][CallLowering] Add support for splitting types according to calling conventions. · fbaf425b
  Amara Emerson authored Sep 03, 2019
  fbaf425b
- [MC] Pass through .code16/32/64 and .syntax unified for COFF · b2d10cf2
  Reid Kleckner authored Sep 03, 2019
  b2d10cf2
- [AArch64][GlobalISel] Don't import i64imm_32bit pattern at -O0 · 15036acb
  Jessica Paquette authored Sep 03, 2019
  15036acb
- [SVE][Inline-Asm] Fix -Wimplicit-fallthrough in AArch64ISelLowering.cpp · 7b5c6b8d
  Kerry McLaughlin authored Sep 03, 2019
  7b5c6b8d
- [X86] Merge 2 consecutive HasInt256 branches. NFCI. · 99525bbe
  Simon Pilgrim authored Sep 03, 2019
  99525bbe
- [SystemZ] Recognize INLINEASM_BR in backend. · a0a81173
  Jonas Paulsson authored Sep 03, 2019
  a0a81173
- [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands · 2f3574c1
  David Green authored Sep 03, 2019
  2f3574c1
- [SystemZ] Add support for fentry. · f1241581
  Jonas Paulsson authored Sep 03, 2019
  f1241581
- [ARM] Invert CSEL predicates if the opposite is a simpler constant to materialise · 61973d97
  David Green authored Sep 03, 2019
  61973d97
- [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions. · 57cc65ff
  David Green authored Sep 03, 2019
  57cc65ff
- [mips] Switch to the `.text` section after emitting asm file preamble · 25d5b545
  Simon Atanasyan authored Sep 03, 2019
  25d5b545
- [ARM] Fix MVE ldst offset ranges · 3e8d5f33
  David Green authored Sep 03, 2019
  3e8d5f33
- [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings · 3be2df24
  Oliver Stannard authored Sep 03, 2019
  3be2df24
- Bug fix on function epilog optimization (ARM backend) · 39bf484d
  Oliver Stannard authored Sep 03, 2019
  39bf484d
- [ARM] Select vmla · 8b2df85d
  Sam Tebbs authored Sep 03, 2019
  8b2df85d
- [X86] Simplify the setOperationAction handling for fp_to_uint by improving the... · b9151090
  Craig Topper authored Sep 03, 2019
  b9151090
- [X86] Don't use Expand for i32 fp_to_uint on SSE1/2 targets on 32-bit target. · 9dc8c448
  Craig Topper authored Sep 03, 2019
  9dc8c448
- [X86] Custom promote i32->f80 uint_to_fp on AVX512 64-bit targets. · dcecc7ea
  Craig Topper authored Sep 03, 2019
  dcecc7ea
Sep 02, 2019
- [X86] Enable fp128 as a legal type with SSE1 rather than with MMX. · 45cd1851
  Craig Topper authored Sep 02, 2019
  45cd1851
- [ARM] Use MQPR not QPR for MVE registers · a95ec59f
  David Green authored Sep 02, 2019
  a95ec59f
- [SystemZ] Support constrained fpto[su]i intrinsics · b21e2457
  Ulrich Weigand authored Sep 02, 2019
  b21e2457
- [SVE][Inline-Asm] Support for SVE asm operands · da4ef9b4
  Kerry McLaughlin authored Sep 02, 2019
  da4ef9b4
- [X86] getPMOVMSKB - add MVT::v64i8 handling and remove from combineBitcastvxi1. NFCI. · fb5661a8
  Simon Pilgrim authored Sep 02, 2019
  fb5661a8
- Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in... · 6e18266a
  Jay Foad authored Sep 02, 2019
  6e18266a
- [AMDGPU][MC][GFX10] Corrected constant bus checks to exclude null · 4aa90ea5
  Dmitry Preobrazhensky authored Sep 02, 2019
  4aa90ea5