Commits · e82e4fa7ef717b95eb3abf45a6f2a3571e6bc468 · Roger Ferrer / llvm-epi · GitLab

May 13, 2022
- [MIPS} Address ISel failures for 64 bit fpus in microMIPS · e82e4fa7
  Simon Dardis authored May 01, 2022
  e82e4fa7
May 12, 2022
- [MIPS] Correct the implementation of the msub optimization · a35add4c
  Simon Dardis authored May 01, 2022
  a35add4c
- [AArch64] Add `foldADCToCINC` DAG combine. · 0298cce2
  Karl Meakin authored May 12, 2022
  0298cce2
- [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`. · d29fc6e7
  Karl Meakin authored May 12, 2022
  d29fc6e7
- [RISCV] Extend dataflow workaround from D119518 to fallthrough blocks · 52b5f1f7
  Philip Reames authored May 12, 2022
  52b5f1f7
- [RISCV] Use tail agnostic policy when selecting riscv_fma_vl to instructions · 40e96545
  Craig Topper authored May 11, 2022
  40e96545
- [AArch64] Preserve chain when lowering fixed length load to SVE (PR55281) · 44d85259
  Nikita Popov authored May 12, 2022
  44d85259
- [AArch64] Stop creating unnecessary label MCSymbols for each Windows unwind opcode. NFC. · 2d8ce08b
  Martin Storsjö authored Nov 11, 2021
  2d8ce08b
- [AMDGPU][NFC] Remove unused function. · bf5fc0d6
  Ivan Kosarev authored May 12, 2022
  bf5fc0d6
- [AMDGPU][GFX10] Support base+soffset+offset SMEM stores. · cb67b2cc
  Ivan Kosarev authored May 12, 2022
  cb67b2cc
- [BPF] Implement mod operation · 50f5cef3
  Jim Lin authored May 11, 2022
  50f5cef3
- [LoongArch] Check msb is not less than lsb for the bstr{ins/pick}.{w/d} instructions · 24532d05
  Weining Lu authored May 03, 2022
  24532d05
- [MIPS] Remove an incorrect microMIPS instruction alias · ba1c70c6
  Simon Dardis authored May 08, 2022
  ba1c70c6
May 11, 2022
- [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic · 2db70021
  Austin Kerbow authored Mar 24, 2022
  2db70021
- [RISCV] Enable subregister liveness tracking for RVV. · ed242b54
  Craig Topper authored May 11, 2022
  ed242b54
- [RISCV] Fold addiw from (add X, (addiw (lui C1, C2))) into load/store address · 5c7ec998
  Craig Topper authored May 11, 2022
  5c7ec998
- [RISCV] Add caching to the gather/scatter to strided load/store conversion. · f499ec6b
  Craig Topper authored May 11, 2022
  f499ec6b
- [RISCV] Move implementation of getVLOpNum and getSEWOpNum from... · 09f48c6b
  Craig Topper authored May 11, 2022
  09f48c6b
- [RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd. · 0ebb02b9
  Craig Topper authored May 11, 2022
  0ebb02b9
- [RISCV] Add a DAG combine to pre-promote (i32 (and (srl X, Y), 1)) with Zbs on RV64. · 07817427
  Craig Topper authored May 11, 2022
  07817427
- [riscv] Canonicalize vsetvli (vsetvli avl, vtype1) vtype2 transitionsas reviewed · 72925d98
  Philip Reames authored May 11, 2022
  72925d98
- [NFC] Change comment number in aarch64 isel · e6635377
  Alban Bridonneau authored May 11, 2022
  
  e6635377
- [DirectX backend] Add pass to emit dxil metadata. · 0c7f7f1b
  python3kgae authored May 07, 2022
  0c7f7f1b
- [AMDGPU] gfx11 Decode wider instructions. NFC · a0a406b2
  Joe Nash authored Apr 21, 2022
  a0a406b2
- [AMDGPU] gfx11 subtarget features & early tests · 18ed279a
  Joe Nash authored Apr 14, 2022
  18ed279a
- [riscv] Prefer to use previous VL for scalar move instructionsK · cc0283a6
  Philip Reames authored May 11, 2022
  cc0283a6
- [RISCV][NFC] Rename variable to appease code style · 27c7e922
  Fraser Cormack authored May 11, 2022
  
  27c7e922
- [RISCV][NFC] Move variable down closer to its first use · 874b802a
  Fraser Cormack authored May 11, 2022
  
  874b802a
- [SelectionDAG][VP] Rename VP sext/zext/trunc ISD opcodes · c1d48b35
  Fraser Cormack authored May 10, 2022
  c1d48b35
- [DirectX backend] Add pass to lower llvm intrinsic into dxil op function. · 85285be9
  Xiang Li authored May 02, 2022
  85285be9
- [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF. · 4537aae0
  Yeting Kuo authored May 08, 2022
  4537aae0
- [RISCV] Add rvv codegen support for vp.fpext. · 2509dcd5
  Jianjian GUAN authored Apr 18, 2022
  2509dcd5
- [X86] Fix 80 column violation in X86InstrInfo.cpp. NFC · cb22cb26
  Mingming Liu authored May 10, 2022
  cb22cb26
- Revert "[NFC] Run clang-format on llvm/lib/Target/X86/X86InstroInfo.cpp" · 852f3d99
  Mingming Liu authored May 10, 2022
  852f3d99
- [NFC] Run clang-format on llvm/lib/Target/X86/X86InstroInfo.cpp · 8bef5476
  Mingming Liu authored May 10, 2022
  8bef5476
- [PowerPC] Fix PPCISD::STBRX selection issue on A2 · 289236d5
  Ting Wang authored May 10, 2022
  289236d5
- [BPF] Mark FI_ri as isPseudo to avoid assertion during disassembly · 8a633261
  Eduard Zingerman authored May 10, 2022
  8a633261
- [Peephole-opt][X86] Enhance peephole opt to see through SUBREG_TO_REG · fc58d7a3
  Mingming Liu authored May 10, 2022
  fc58d7a3
- [riscv] Consolidate logic for SEW/VL operand offset calculations [nfc] · 7731935f
  Philip Reames authored May 10, 2022
  
  7731935f
May 10, 2022
- [riscv] Minor style cleanup so that code more obviously matches comments [nfc] · 41305231
  Philip Reames authored May 10, 2022
  
  41305231