Commits · e8bce83996313ed3f4f5fce43107530d49fc3b64 · Roger Ferrer / llvm-epi · GitLab

Apr 23, 2021
- [X86] Enable compilation of user interrupt handlers. · e8bce839
  Wang, Pengfei authored Apr 23, 2021
  e8bce839
- AMDGPU: Restore atomic fp feature on FP atomic instruction definitions · ed633a1d
  Matt Arsenault authored Apr 09, 2021
  ed633a1d
- [IR][sanitizer] Add module flag "frame-pointer" and set it for cc1 -mframe-pointer={non-leaf,all} · 2786e673
  Fangrui Song authored Apr 22, 2021
  2786e673
- [RISCV] [1/2] Add IR intrinsic for Zbp extension · b49337bb
  Levy Hsu authored Apr 22, 2021
  b49337bb
- llvm-objdump: add --rpaths to macho support · 86b98c60
  Keith Smiley authored Apr 19, 2021
  86b98c60
- [WebAssembly] Fix fixEndsAtEndOfFunction for delegate · c390621a
  Heejin Ahn authored Apr 22, 2021
  c390621a
- [WebAssembly] Serialize params/results in MachineFunctionInfo · b3e88ccb
  Heejin Ahn authored Apr 21, 2021
  b3e88ccb
- [RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases. · 5185b529
  Craig Topper authored Apr 22, 2021
  5185b529
Apr 22, 2021
- [Hexagon] Improve lowering of returns of i1 · 06234f75
  Krzysztof Parzyszek authored Apr 22, 2021
  06234f75
- [GVN] Generate LE and BE check lines (NFC) · 1d96107c
  Nikita Popov authored Apr 22, 2021
  1d96107c
- [GVN] Regenerate test checks (NFC) · 9d1b2bc7
  Nikita Popov authored Apr 22, 2021
  
  9d1b2bc7
- [Hexagon] Use 'vnot' instead of 'not' in patterns with vectors · ab9521aa
  Krzysztof Parzyszek authored Apr 22, 2021
  ab9521aa
- [GlobalOpt] Don't replace alias with aliasee if aliasee is interposable · 16ff1a70
  Arthur Eubanks authored Apr 20, 2021
  16ff1a70
- [AArch64] Improve vector reverse lowering · c0bf5929
  David Green authored Apr 22, 2021
  c0bf5929
- [SCEV] Compute ranges for lshr recurrences · 424d6cb9
  Philip Reames authored Apr 22, 2021
  424d6cb9
- Revert "[instcombine] Exploit UB implied by nofree attributes" · 15e19a25
  Philip Reames authored Apr 22, 2021
  15e19a25
- [RISCV] Add IR intrinsics for vmsge(u).vv/vx/vi. · e01c419e
  Craig Topper authored Apr 22, 2021
  e01c419e
- [RISCV] Add missing tests for vector type for second operand of vmsgt and vmsgtu IR intrinsics. · d77d56ac
  Craig Topper authored Apr 22, 2021
  d77d56ac
- [RISCV] Support vector type for second operand of vmfge and vmfgt IR intrinsics. · 9524a055
  Craig Topper authored Apr 22, 2021
  9524a055
- [RISCV] Turn splat shuffles of vector loads into strided load with stride of x0. · 70254ccb
  Craig Topper authored Apr 22, 2021
  70254ccb
- [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. · 77f14c96
  Craig Topper authored Apr 22, 2021
  77f14c96
- [Hexagon] Add HVX intrinsics for conditional vector loads/stores · deda60fc
  Krzysztof Parzyszek authored Apr 22, 2021
  deda60fc
- [dfsan] Track origin at loads · 7fdf2709
  Jianzhou Zhao authored Apr 21, 2021
  7fdf2709
- [x86] remove stale comment from test file; NFC · 11232037
  Sanjay Patel authored Apr 22, 2021
  
  11232037
- [SLP]Skip undefs trying to find perfect/shuffled tree entries matching. · 18c61fc4
  Alexey Bataev authored Apr 22, 2021
  18c61fc4
- [llvm-profgen] A couple tweaks to the testing harness. · aaf120b5
  Hongtao Yu authored Apr 21, 2021
  aaf120b5
- [Hexagon] Unmasked and masked load pair to dame bae -? one load and selects · f3451162
  Coplin, Jared authored Apr 22, 2021
  
  f3451162
- [AArch64] Block tryCombineToBSL combines for vectors wider than NEON · 528ee161
  Joe Ellis authored Apr 22, 2021
  528ee161
- [LoopVectorize] Fix bug where predicated loads/stores were dropped · 2c551aed
  Joe Ellis authored Mar 31, 2021
  2c551aed
- [SLP]Improve cost model for the vectorized extractelements. · e99b98cb
  Alexey Bataev authored Apr 06, 2021
  e99b98cb
- [LoopIdiom] Added testcase for double memset (fixed in LLVM 12); NFC · f070956c
  Dávid Bolvanský authored Apr 22, 2021
  
  f070956c
- Revert "[Hexagon] Masked and unmasked load to same base -> load and two selects" · e8d04754
  Krzysztof Parzyszek authored Apr 22, 2021
  e8d04754
- AArch64: support mixed-size fp <-> int conversions in GlobalISel. · 2e72f6b5
  Tim Northover authored Apr 20, 2021
  
  2e72f6b5
- AArch64: expand G_DIVREM operations in GlobalISel · ac1647cc
  Tim Northover authored Apr 20, 2021
  ac1647cc
- [Hexagon] Masked and unmasked load to same base -> load and two selects · 96dc8d7e
  Coplin, Jared authored Apr 22, 2021
  
  96dc8d7e
- [X86] Regenerate atomic-eflags-reuse.ll · 05953cf6
  Simon Pilgrim authored Apr 22, 2021
  
  05953cf6
- [InstCombine][NFC] Use --check-globals flag in tests. · d944b1e0
  Dawid Jurczak authored Apr 22, 2021
  d944b1e0
- [DAGCombiner] Allow operand of step_vector to be negative. · 978eb3f1
  Jun Ma authored Apr 19, 2021
  978eb3f1
- [Bitcode] Ensure DIArgList in bitcode has no null or forward metadata refs · e5d844b5
  Stephen Tozer authored Apr 21, 2021
  e5d844b5
- [X86][AVX] Add PR49971 test case · e28ae5e5
  Simon Pilgrim authored Apr 22, 2021
  e28ae5e5